A semiconductor device polysilicon resistor formation method is provided. A third ion implantation and a fourth ion implantation are performed in a polysilicon resistor region, so that a high-resistance polysilicon resistor can be formed without an additional mask process.

A method of manufacturing a semiconductor device includes forming a gate structure over an active region of a substrate, the gate structure comprising a first section and a second section. The first section and the second section dividing the active region into a first source/drain region between the first section and the second section, and a pair of second source/drain regions arranged on opposite sides of the gate structure. The method further includes forming a conductive field plate over the substrate, the field plate extending between the first section and the second section and overlapping an edge of the active region. The method further includes implanting a first well in the substrate, wherein the first well overlaps the edge of the active region. The method further includes forming an isolation structure in the substrate, wherein the conductive field plate extends over the isolation structure.

A switching LDMOS device is formed first well in a semiconductor substrate that includes an LDD region and a first body doped region; a first heavily doped region serving as a source region is provided in the LDD region, and a second heavily doped region serving as a drain region is provided in the first body doped region; a channel of the switching LDMOS device is formed at a surface layer of the semiconductor substrate between the LDD region and the body doped region and below the gate structure; and one side of the LDD region and one side of the body doped region which are away from the gate structure both are provided with a field oxide or STI, and one side of the field oxide or STI is in contact with the first heavily doped region or the second heavily doped region.

A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film.

The present disclosure relates to a transistor device having source and drain regions within a substrate. A gate electrode is between the source and drain regions. A spacer has a lower lateral portion along an upper surface of the substrate between the gate electrode and the drain region, a vertical portion extending along a sidewall of the gate electrode, and an upper lateral portion extending from the vertical portion to an outermost sidewall directly over the gate electrode. A field plate is disposed along an upper surface and a sidewall of the spacer and is separated from the gate electrode and the substrate by the spacer. A first ILD layer overlies the substrate, the gate electrode, and the field plate. A first conductive contact has opposing outermost sidewalls intersecting a first horizontally extending surface of the field plate between the gate electrode and the drain region.

A method for forming a semiconductor structure includes providing a substrate including a first region with a first gate structure and a second region with a second gate structure. First to third dielectric layers are formed on the substrate. The third dielectric layer is patterned to form a first portion in the first region and a second portion in the second region. The second region is covered and at least a portion of the first portion is removed to form a first mask. The second dielectric layer is pattern by using the first mask and the second portion as the second mask to expose a portion of the first dielectric layer. The portion of the first dielectric layer is removed to form a first stacked spacer on the first gate structure and a second stacked spacer on the second gate structure.

The present application provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof. The transistor comprising: a semiconductor substrate having a doping region, wherein the doping region comprises a first well region and a second well region with opposite doping types; a source region, a drain region, a shallow trench isolation (STI) structure comprising a laminated structure having an alternate layers of insulating material and ferroelectric material, a gate, a contact hole, and a metal layer. The LDMOS transistor simultaneously increases breakdown voltage (BV) and reduces on-resistance (R.sub.on).

Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

A semiconductor device may include a first device on a first portion of a substrate, a second device on a second portion of the substrate, and a third device on a third portion of the substrate. The third device may include an oxide layer that is formed from an oxide layer that is a sacrificial oxide layer for the first device and the second device. The third device may include a gate provided on the oxide layer, a set of spacers provided on opposite sides of the gate, and a source region provided in the third portion of the substrate on one side of the gate. The third device may include a drain region provided in the third portion of the substrate on another side of the gate, and a protective oxide layer provided on a portion of the gate and a portion of the drain region.

An LDMOS device and a method for forming the LDMOS device are provided. The LDMOS device includes: a substrate formed with a source region, a drain region and a drift region; a gate structure; a silicide block layer; a first conductive structure having one end electrically connected with the source region, a second conductive structure having one end electrically connected with the drain region; a first metal interconnecting structure electrically connected with the other end of the first conductive structure, a second metal interconnecting structure electrically connected with the other end of the second conductive structure; a third conductive structure having one end disposed on a surface of the silicide block layer; and a third metal interconnecting structure electrically connected with the other end of the third conductive structure. The LDMOS device has increased breakdown voltage, and reduced on-resistance, and its preparation process is safer and easier to control.