A semiconductor device is provided. The semiconductor device includes a base substrate; a first well region and a second well region in the base substrate; a gate electrode structure, sidewall spacers, a doped source layer and a doped drain layer over the base substrate; a dielectric layer on the base substrate; and an isolation layer in the dielectric layer. The dielectric layer covers sidewalls of the sidewall spacers, the doped source layer and the doped drain layer, and exposes a top surface of the gate electrode structure. The isolation layer is in the gate electrode structure of the second well region and the base substrate of the second well region, and adjacent to the sidewalls of the sidewall spacer over the second well region.

A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

A high voltage transistor structure including a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source and drain region, and a second source and drain region is provided. The first and second drift regions are disposed in the substrate. The first and second cap layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located over at least a portion of the first drift region and at least a portion of the second drift region. The first and second source and drain regions are respectively disposed in the first and second drift regions and located on two sides of the gate structure. The size of the first drift region and the size of the second drift region are asymmetric.

A semiconductor device is disclosed that includes a first region of a first conductivity type that includes a drain, a region of a second conductivity type abutting the first region in a lateral direction and a vertical direction to form an interface between the first conductivity type and the second conductivity type, wherein the drain region is spaced apart from the interface. A source region of the first conductivity type abuts the second region in the lateral direction and vertical directions. A control gate structure includes a conductive layer that is spaced apart from the drain region by a first dimension in the lateral direction. A shallow trench isolation (STI) region having a second dimension in the lateral direction is disposed at a location of the first region between the source and drain regions, wherein the second dimension is less than one-half of the first dimension.

The present disclosure relates to a high voltage transistor device having a thin polysilicon film field plate, and an associated method of formation. In some embodiments, the high voltage transistor device has a gate electrode disposed between source and drain regions and separated from a substrate by a gate dielectric. A spacer is disposed along an upper surface of the substrate. The spacer extends along a first gate sidewall closer to the drain region, crosses over an upper edge of the gate electrode, and further extends laterally to cover a portion of an upper surface of the gate electrode. A field plate including a polysilicon thin film is disposed along upper and sidewall surfaces of the spacer so that the polysilicon thin film is separated from the gate electrode and the substrate by the spacer. The thin polysilicon film field plate improves the breakdown voltage of the transistor device.

Provided is a semiconductor device and a method of manufacturing the same and, more particularly, to a semiconductor device and a method of manufacturing the same seeking to simplify the manufacturing process and consequently improve efficiency and reliability by forming an isolation region (191) including a pre-DTI region (1911) and a DTI region (1913) in and/or on a substrate before depositing an interlayer dielectric, thereby avoiding a need for a separate etch stop layer.

A method is provided for fabricating an LDMOS transistor. The method includes providing a base substrate. The method also includes forming a first well area doped with a first well ion in the base substrate. In addition, the method includes forming a second well area doped with a second well ion in the base substrate, where the second well area includes a first region adjacent to the first well area. Moreover, the method includes forming a first ion doping region doped with first ions in the first well area and the first region, where a type of the first ions is the same as a type of the first well ion and opposite to a type of the second well ion. Further, the method includes forming a gate structure on part of the first well area and part of the first region.

Disclosed are a high voltage semiconductor device and a method of manufacturing the high voltage semiconductor device. More specifically, a high voltage semiconductor device and a method of manufacturing the high voltage semiconductor device omit a conventional deep NDT region in a body region of the device, and include a HV-NLDD region to minimize the width of the body region, thereby improving integration and on-resistance of the semiconductor device.

Disclosed is an LDMOS device comprising a drift region formed by a selected area of a doped layer of a first conductivity type on a semiconductor substrate, a gate structure comprising a gate dielectric layer and a gate conductive layer which are sequentially formed on a surface of the doped layer of the first conductivity type, a doped self-aligned channel region of a second conductivity type, and a doped layer formed by tilted ion implantation with a first side face of the gate structure as a self-alignment condition. A method for manufacturing an LDMOS device is further disclosed. The channel length is not affected by lithography and thus can be minimized to fulfill an ultralow specific-on-resistance, and the distribution uniformity of the channel length can be improved, so that the performance uniformity of the device is improved.

The present disclosure provides a manufacture method of an LDMOS. The manufacture method includes: forming a drift region in a substrate; forming a gate structure on the substrate, the gate structure defining a source region and a drain region which are separated from each other, and the gate structure including a gate oxide layer and a gate conductor layer which are successively stacked on the substrate; forming a first doped region in the source region, wherein the first doped region is surrounded by the drift region; forming a first barrier layer with a first opening on the source region and in connect with sidewall of the gate structure; forming a first implantation region in the source region through self-aligned implantation on the basis of the first opening of the first barrier layer; and forming a second implantation region and a third implantation region respectively.