Devices and methods for providing a power transistor structure with a shallow source region include implanting a dopant of a first dopant polarity into a drift region on a source side of a gate structure to form a body region, the body region being self-aligned to, and extending under, the gate structure, and producing a shallow body region wherein the source side hybrid contact mitigates punch through of the shallow self-aligned body region and suppresses triggering of a parasitic bipolar. A retrograde body well, of the first dopant polarity, may be disposed beneath, and noncontiguous with, the shallow self-aligned body region, wherein the retrograde body well improves the electric field profile of the shallow self-aligned body region. A variety of power transistor structures are produced from such devices and methods.

A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

A trench power MOSFET includes a body region disposed on a semiconductor substrate, a trench passing through the body region, an top electrode and a bottom electrode spaced apart from each other in a vertical direction in the trench, an inter-electrode dielectric layer disposed between the top electrode and the bottom electrode, and a plurality of dielectric layers, disposed between a sidewall of the trench and the bottom electrode, comprising a first oxide layer disposed on the sidewall of the trench, an barrier layer disposed on the first oxide layer, and a second oxide layer disposed on the barrier layer. The barrier layer is formed of a material different from materials of the first and second oxide layers.

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

Implementations of the present disclosure generally relate to methods for forming a transistor. More specifically, implementations described herein generally relate to methods for forming a source/drain contact. In one implementation, the method includes forming a trench in a dielectric material to expose a source/drain region of a transistor, performing a pre-clean process on the exposed source/drain region, forming a doped semiconductor layer on the source/drain region by an epitaxial deposition process, and fill the trench with a conductor. The doped semiconductor layer has a lower electrical resistance than the source/drain region due to a higher dopant concentration in the doped semiconductor layer. As a result, the contact resistance of the source/drain contact is reduced.

A manufacturing method of an LDMOS device comprises: obtaining a wafer formed with a doped region having a first conductivity type, wherein a top buried layer is formed inside the doped region having the first conductivity type, and a field oxide insulation layer structure is formed on the top buried layer; disposing a trench on the doped region having the first conductivity type, wherein the trench extends to the top buried layer and the field oxide insulation layer structure such that a portion of the top buried layer is removed; injecting an ion of a second conductivity type to form a well region below the trench; and forming a doped source region in the well region. The first conductivity type and the second conductivity type are opposite conductivity types.

A semiconductor structure and a method for forming same are provided. The forming method includes: forming an initial gate covering a second region and extending to cover a part of a first region; forming a drain region in the first region on a side of the initial gate; forming a protective film conformally covering the drain region, a top surface and a side wall of the initial gate, and a surface of a base; removing a partial width of the protective film and a partial width of the initial gate of the second region to form a protective layer, a gate, and an opening enclosed by a side wall of the gate and a partial width of the base of the second region, the gate covering a junction between the second region and the first region; performing first doping on the base under the opening to form a body region; performing second doping on the base under the opening to form a doped region, the doped region including a sacrificial doped region and a source region between the sacrificial doped region and the gate; and etching the sacrificial doped region and a partial thickness of the base under the sacrificial doped region by using the protective layer as a mask, and forming a trench in the body region, a side wall of the trench exposing the source region. Embodiments of the present disclosure can improve performance of an LDMOS device.

A MOSFET structure and a manufacturing method thereof are provided. The structure includes a substrate, a well region of a first conductivity type, a first trench formed on a surface of the well region of the first conductivity type and extending downwards to a well region of a second conductivity type, a source disposed in the well region of the second conductivity type and under the first trench, a gate oxide layer disposed on an inner surface of the first trench, a polysilicon gate disposed on the gate oxide layer, a conductive plug extending downwards from above the first trench and being in contact with the well region of the second conductivity type after extending through the source, an insulation oxide layer filled in the first trench between the conductive plug and the polysilicon gate, and a drain disposed outside the first trench and obliquely above the source.

A semiconductor device includes a transistor in a semiconductor body having a main surface. The transistor includes a source region; a drain region; a body region; a drift zone; a gate electrode at the body region, the body region and the drift zone being disposed along a first direction between the source region and the drain region, and the first direction being parallel to the main surface; a field plate disposed in each of a plurality of field plate trenches, each of the field plate trenches having a longitudinal axis extending along the first direction; and a field dielectric layer between the field plate and the drift zone, a thickness of the field dielectric layer at a bottom of each of the field plate trenches gradually increases along the first direction, the thickness being measured along a depth direction of the plurality of field plate trenches.