A semiconductor device includes: a substrate, a gate structure on the substrate, and a spacer adjacent to the gate structure, in which the spacer extends to a top surface of the gate structure, a top surface of the spacer includes a planar surface, the spacer encloses an air gap, and the spacer is composed of a single material. The gate structure includes a high-k dielectric layer, a work function metal layer, and a low resistance metal layer, in which the high-k dielectric layer is U-shaped. The semiconductor device also includes an interlayer dielectric (ILD) layer around the gate structure and a hard mask on the spacer, in which the top surface of the hard mask is even with the top surface of the ILD layer.

A method of manufacturing a semiconductor device includes providing a semiconductor substrate having a main surface and a gate electrode which is within a trench between neighboring semiconductor mesas. The gate electrode is electrically insulated from the neighboring semiconductor mesas by respective dielectric layers. A respective pillar on each of the neighboring semiconductor mesas is formed, leaving an opening between the pillars above the trench. Dielectric contact spacers are formed in the opening along respective pillar side walls to narrow the opening above the gate electrode. A conductor is formed, having an interface with the gate electrode. The interface extends along an extension of the gate electrode, and the conductor has a conductivity greater than the conductivity of the gate electrode.

A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially overlapping the body region and insulated from the semiconductor body by a gate dielectric layer; a source diffusion region of a second conductivity type formed in the body region on a first side of the gate electrode; a trench formed in the semiconductor body on a second side, opposite the first side, of the gate electrode, the trench being lined with a sidewall dielectric layer; and a doped sidewall region of the second conductivity type formed in the semiconductor body along the sidewall of the trench where the doped sidewall region forms a vertical drain current path for the transistor.

A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.

A shielded gate trench MOSFET device structure is provided. The device structure includes MOS gate trenches and p body contact trenches formed in an n type epitaxial silicon layer overlying an n+ silicon substrate. Each MOS gate trench includes a gate trench stack having a lower n+ shield poly silicon layer separated from an upper n+ gate poly silicon layer by an inter poly dielectric layer. The upper and lower poly silicon layers are also laterally isolated at the areas where the lower poly silicon layer extends to silicon surface by selectively removing portion of the upper poly silicon and filling the gap with a dielectric material. The method is used to form both MOS gate trenches and p body contact trenches in self-aligned or non self-aligned shielded gate trench MOSFET device manufacturing.

A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions disposed above the drain region, a plurality of gate insulator regions each disposed about a periphery of a respective one of the plurality of gate regions, a plurality of source regions disposed in recessed mesas between the plurality of gate insulator regions, a plurality of body regions disposed in recessed mesas between the plurality of gate insulator regions and between the plurality of source regions and the drain region. The MOSFET also includes a plurality of body contact regions disposed in the each body region adjacent the plurality of source regions, a plurality of source/body contact spacers disposed between the plurality of gate insulator regions above the recessed mesas, a source/body contact disposed above the source/body contact spacers, and a plurality of source/body contact, plugs disposed between the source/body contact spacers and coupling the source/body contact to the plurality of body contact regions and the plurality of source regions.

Self-aligned FET devices and associated fabrication methods are disclosed herein. A disclosed process for forming a FET includes forming a first mask, implanting a deep well region in a drift region using the first mask, forming a spacer in contact with the first mask, and implanting a shallow well region in the drift region using the first mask and the spacer. A disclosed FET includes a drift region, a shallow well region, a deep well region located between the shallow well region and the drift region, and a junction field effect region: in contact with the shallow well region, the drift region, and the deep well region; and having a junction field effect doping concentration of the first conductivity type. The FETs can include a hybrid channel formed by a portion of the junction field effect region, as influenced by the deep well region, and the shallow well region.

A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.

A manufacturing method of a semiconductor power device includes the following steps: An n-type substrate is etched in a self-aligning manner using a first insulating layer, a second insulating layer, and a third insulating layer as a mask to form a second groove in the n-type substrate. A fourth insulating layer and a gate are formed in the second groove.

A MOS transistor of vertical-conduction, trench-gate, type, including a first and a second spacer adjacent to portions of a gate oxide of the trench-gate protruding from a semiconductor substrate, the first and second spacers being specular to one another with respect to an axis of symmetry; enriched P+ regions are formed by implanting dopant species within the body regions using the spacers as implant masks. The formation of symmetrical spacers makes it possible to form source, body and body-enriched regions that are auto-aligned with the gate electrode, overcoming the limitations of MOS transistors of the known type in which such regions are formed by means of photolithographic techniques (with a consequent risk of asymmetry).