A trench power transistor includes a semiconductor body having opposite first and second surfaces, and including at least one active region. Such region includes a trench electrode structure, a well, and a source. The trench electrode structure has an electrode trench recessed from the first surface, and includes first, second, and third insulating layers sequentially disposed over bottom and surrounding walls of the electrode trench, a shield electrode enclosed by the third insulating layer, a fourth insulating layer disposed on the first, second, and third insulating layers, and a gate electrode surrounded by the fourth insulating layer. The second insulating layer made of a nitride material and the fourth insulating layer are different in material. A production method of the transistor is also disclosed.

A semiconductor device, comprising: a substrate; an active gate trench in the substrate; a source polysilicon pickup trench in the substrate; a polysilicon electrode disposed in the source polysilicon pickup trench; a gate pickup trench in the substrate; a first conductive region and a second conductive region disposed in the gate pickup trench, the first conductive region and the second conductive region being separated by oxide, wherein at least a portion of the oxide surrounding the first conductive region in the gate pickup trench is thicker than at least a portion of the oxide under the second conductive region; and a body region in the substrate.

A semiconductor body having a drift region layer, a body region layer adjoining the drift region layer, and a source region layer adjoining the body region layer and forming a first surface of the semiconductor body is provided. At least two trenches extend from the first surface of the semiconductor body through the source region layer and the body region layer. In each of the trenches a gate electrode and a gate dielectric are formed. Diode regions are directly adjacent to each of the at least two trenches. The diode regions extend from the first surface of the semiconductor body through the source region layer and the body region layer. The diode regions include a first region and a second region. A doping concentration in the diode regions varies such that a doping concentration is higher near the first surface than at the bottom of the trench.

The present disclosure discloses a self-aligned silicon carbide MOSFET device with an optimized P.sup.+ region and a manufacturing method thereof. The self-aligned silicon carbide MOSFET device is formed by a plurality of silicon carbide MOSFET device cells connected in parallel, and these silicon carbide MOSFET device cells are arranged evenly. The silicon carbide MOSFET device cell comprises two source electrodes, one gate electrode, one gate oxide layer, two N.sup.+ source regions, two P.sup.+ contact regions, two P wells, one N.sup. drift layer, one buffer layer, one N.sup.+ substrate, one drain electrode and one isolation dielectric layer. By optimizing the P.sup.+ region, the present disclosure forms a good source ohmic contact, reduces the on-resistance, and also shorts the source electrode and the P well to prevent the parasitic transistor effect of the parasitic NPN and PiN, which may take both conduction characteristics and the breakdown characteristics of the device into consideration, and may be applied to a high voltage, high frequency silicon carbide MOSFET device. The self-aligned manufacturing method used in the present disclosure simplifies the process, controls a size of a channel accurately, and may produce a lateral and vertical power MOSFET.

A transistor device includes a channel region including a portion located in a vertical sidewall of semiconductor material and an extended drain region including a portion located in a lower portion of the semiconductor material. In one embodiment, a control terminal of the transistor device is formed by forming a conductive sidewall spacer structure adjacent to the sidewall and a field plate for the transistor device is formed by forming a second conductive sidewall spacer structure.

Semiconductor device structures comprising a spacer feature having multiple spacer layers are provided. In one example, a semiconductor device includes an active area on a substrate, the active area comprising a source/drain region, a gate structure over the active area, the source/drain region being proximate the gate structure, a spacer feature having a first portion along a sidewall of the gate structure and having a second portion along the source/drain region, wherein the first portion of the spacer feature comprises a bulk spacer layer along the sidewall of the gate structure, wherein the second portion of the spacer feature comprises the bulk spacer layer and a treated seal spacer layer, the treated seal spacer layer being disposed along the source/drain region and between the bulk spacer layer and the source/drain region, and a contact etching stop layer on the spacer feature.

A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.

A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.

A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.