A shield trench power device such as a trench MOSFET or IGBT includes a substrate or an epitaxial layer of silicon, silicon carbide, gallium nitride, or gallium arsenide and employs an in-trench structure including a gate structure and an underlying polysilicon or oxide shield region that contacts a shield region in an epitaxial or crystalline layer of the device. The poly silicon region may be laterally confined by spacers in a gate trench and may contact or be isolated from the underlying shield region. Alternatively, the polysilicon region may be replaced with an insulating region.

An integrated circuit includes an epitaxial layer over a semiconductor substrate. The epitaxial layer has a first conductivity type and a top surface. First, second and third trenches are located in the epitaxial layer. The trenches respectively include first, second and third field plates. First and second body members are located within the epitaxial layer and have a different second conductivity type. The first body member is located between the first and second trenches, and the second body member is located between the second and third trenches. The first body member extends a first distance between the top surface and the substrate, and the second body member extends a lesser second distance between the top surface and the substrate.

The fabrication method for a silicon carbide semiconductor device according to this disclosure includes a step of forming a dielectric film over part of a silicon carbide layer, a step of forming an ohmic electrode adjoining the dielectric film on the silicon carbide layer, a step of removing an oxidized layer on the ohmic electrode, a step of forming a mask with its opening on the side opposite to the side where the ohmic electrode is adjoining the dielectric film on the ohmic electrode having the oxidized layer removed and on the dielectric film, and a step of wet etching of a film to be etched with hydrofluoric acid with the mask formed. With the fabrication method for a silicon carbide semiconductor device described in this disclosure, it is possible to fabricate a silicon carbide semiconductor device with reduced failure.

An ion implanted region is formed by implanting Mg ions into a predetermined region of the surface of the first p-type layer. Subsequently, a second n-type layer is formed on the first p-type layer and the ion implanted region. A trench is formed by dry etching a predetermined region of the surface of the second n-type layer until reaching the first n-type layer. Next, heat treatment is performed to diffuse Mg. Thus, a p-type impurity region is formed in a region with a predetermined depth from the surface of the first n-type layer below the ion implanted region. Since the trench is formed before the heat treatment, Mg is not diffused laterally beyond the trench. Therefore, the width of the p-type impurity region is almost the same as the width of the first p-type layer divided by the trench.

A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.

Disclosed is a method for manufacturing a conducting path in a doped region, comprising: forming a dielectric layer on a semiconductor layer which includes the doped region; forming an opening in the dielectric layer; forming a side wall on sidewall of the opening; etching the semiconductor layer through the opening to form a conduction hole extending to the doped region; filling the conduction hole with conductive material to form a conducting path, wherein the side wall reduces a transverse dimension of the conducting path. According to the method for manufacturing the conducting path in the doped region in the present disclosure, by forming the side wall on sidewall of the opening in the dielectric layer, the transverse dimension of the opening in the dielectric layer is reduced, thereby the semiconductor layer is etched with a narrower opening to obtain the conduction hole with a smaller size, device performance is improved.

A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (μm). A width of the unit cell is one of less than and equal to 5.0 micrometers (μm). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.

A semiconductor device is described. The semiconductor device includes: a plurality of stripe-shaped gates formed in a semiconductor substrate; a plurality of needle-shaped field plate trenches formed in the semiconductor substrate between neighboring ones of the stripe-shaped gates; an insulating layer on the semiconductor substrate; and a plurality of contacts extending through the insulating layer and contacting field plates in the needle-shaped field plate trenches. The contacts have a width that is less than or equal to a width of the needle-shaped field plate trenches, as measured in a first lateral direction which is transverse to a lengthwise extension of the stripe-shaped gates. In the first lateral direction, the contacts are spaced apart from the stripe-shaped gates by a same or greater distance than the needle-shaped field plate trenches. Methods of producing the semiconductor device are also described.

A method for manufacturing a semiconductor device is provided. A drift region and a compensation region are formed through a deep trench etching and a filling technology. A plurality of modulation doping regions are formed at a top of the drift region by an epitaxy and an ion implantation. A modulation region is introduced, wherein the modulation region flexibly modifies capacitance characteristics and achieve improved dynamic characteristics.