A semiconductor device includes a semiconductor body and a device cell in the semiconductor body. The device cell includes: drift, source, body and diode regions; a pn junction between the diode and drift regions; a trench with first and second opposing sidewalls and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the trench bottom; a gate electrode in the trench and dielectrically insulated from the source, body, diode and drift regions by a gate dielectric; a further trench extending from a first surface of the semiconductor body into the semiconductor body; a source electrode arranged in the further trench adjoining the source and diode regions. The diode region includes a lower diode region arranged below the trench bottom. The lower diode region has a maximum of a doping concentration distant to the trench bottom.

A method of forming a power semiconductor device is provided. The method includes the step of providing a semiconductor substrate. The semiconductor substrate has an active region and a termination region surrounding the active region. An epitaxial layer is disposed on the semiconductor substrate. The etching process is conducted to the epitaxial layer to form a first trench and a second trench. The first trench is disposed at the active region and the second trench is disposed at the termination region. A second trench width of the second trench is less than a first trench width of the first trench. An oxidation process is conducted to form a dielectric structure. The dielectric structure has a first dielectric layer disposed on the first trench and a dielectric area fully covers a trench area of the second trench.

In a vertical MOSFET in which bottom portions of each gate electrode formed in a ditch are extended toward the drain region, the on resistance is reduced while preventing voltage resistance reduction and switching speed reduction caused by a capacitance increase between the gate and drain. A vertical MOSFET includes first ditches, second ditches, and gate electrodes. The first ditches are formed in an upper surface portion of an epitaxial layer formed over a semiconductor substrate and extend in a second direction extending along a main surface of the semiconductor substrate. The second ditches are formed in bottom surface portions of each of the first ditches and are arranged in the second direction. The gate electrodes are formed in the first ditches and second ditches. The gate electrodes formed in the first ditches include lower electrodes arranged in the second direction.

An electronic device can include a semiconductor layer, an insulating layer overlying the semiconductor layer, and a conductive electrode. In an embodiment, a first conductive electrode member overlies the insulating layer, and a second conductive electrode member overlies and is spaced apart from the semiconductor layer. The second conductive electrode member has a first end and a second end opposite the first end, wherein each of the semiconductor layer and the first conductive electrode member are closer to the first end of the second conductive electrode member than to the second end of the second conductive electrode member. In another embodiment, the conductive electrode can be substantially L-shaped. In a further embodiment, a process can include forming the first and second conductive electrode members such that they abut each other. The second conductive electrode member can have the shape of a sidewall spacer.

A plurality of first trenches is formed in a cell region and a second trench is formed in an outer peripheral region. A gate electrode and a first field plate electrode are formed in each of the plurality of first trenches, and a second field plate electrode is formed in the second trench. For example, in a drift region formed in the outer peripheral region, a p-type column region is formed in a portion sandwiched, in a Y direction, by a portion, which is located between two of the plurality of first trenches arranged next to each other, and the second trench.

A method for forming a semiconductor device includes forming a first insulation layer on a semiconductor substrate and forming a structured etch stop layer. Further, the method includes depositing a second insulation layer after forming the structured etch stop layer and forming a structured mask layer on the second insulation layer. Additionally, the method includes etching portions of the second insulation layer uncovered by the structured mask layer and portions of the first insulation layer uncovered by the structured etch stop layer to uncover at least one of a portion of the semiconductor substrate and an electrode located within a trench. Further, the method includes depositing electrically conductive material to form an electrical contact to at least one of the uncovered electrode and the uncovered portion of the semiconductor substrate.

To provide a semiconductor device having a structure capable of forming a superjunction with less thermal history, a semiconductor device is provided, the semiconductor device including a contact trench formed between two gate trenches, penetrating through a source region, and including its lower end arranged in a base region, and a second conductivity-type protruding portion formed protruding toward a lower side from the lower end of the base region in a region opposite to the lower end of the contact trench, wherein the depth from the upper end of the source region to a lower end of the protruding portion is 3 μm or more, and a carrier concentration Nd in a first conductivity-type region adjacent to the protruding portion in a lateral direction perpendicular to a depth direction and a carrier concentration Na of the protruding portion satisfy a predetermined equation.

A SiC semiconductor device includes SiC chip having main surface that includes first surface, second surface hollowed in thickness direction at first depth outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a transistor structure formed at an inward portion of the first surface, the transistor structure including a trench gate structure that has a second depth less than the first depth and a trench source structure that has a third depth exceeding the second depth and that adjoins the trench gate structure in one direction, and a dummy structure formed at a peripheral edge portion of the first surface, the dummy structure including a plurality of dummy trench source structures which have the third depth and adjoin each other in the one direction.

A device is described herein. The device comprises a unit cell of a silicon carbide (SiC) substrate. The unit cell comprises: a trench in a well region having a second conduction type. The well region is in contact with a region having a first conduction type to form a p-n junction. A width of the trench is less than 1.0 micrometers (μm). A width of the unit cell is one of less than and equal to 5.0 micrometers (μm). The device comprises a source region comprising the first conduction type. The device further comprises a metal oxide semiconductor field effect transistor component. The device described herein comprises a reduced unit cell pitch and reduced channel resistance without any compromise in channel length. The device comprises an ILD opening greater than or equal to width of the trench.

A semiconductor device of an embodiment includes: a first trench in a silicon carbide layer and extending in a first direction; a second trench and a third trench located in a second direction orthogonal to the first direction with respect to the first trench and adjacent to each other in the first direction, n type first silicon carbide region, p type second silicon carbide region on the first silicon carbide region, n type third silicon carbide region on the second silicon carbide region, p type fourth silicon carbide region between the first silicon carbide region and the second trench, and p type fifth silicon carbide region located between the first silicon carbide region and the third trench; a gate electrode in the first trench; a first electrode; and a second electrode. A part of the first silicon carbide region is located between the second trench and the third trench.