Semiconductor structures and methods are provided. A method according to the present disclosure includes providing a workpiece that includes a plurality of active regions including channel regions and source/drain regions, and a plurality of dummy gate stacks intersecting the plurality of active regions at the channel regions, the plurality of dummy gate stacks including a device portion and a terminal end portion. The method further includes depositing a gate spacer layer over the workpiece, anisotropically etching the workpiece to recess the source/drain regions and to form a gate spacer from the gate spacer layer, forming a patterned photoresist layer over the workpiece to expose the device portion and the recessed source/drain regions while the terminal end portion is covered, and after the forming of the patterned photoresist layer, epitaxially forming source/drain features over the recessed source/drain regions.

A semiconductor structure includes a substrate, a semiconductor fin protruding from the substrate, where the semiconductor fin includes semiconductor layers stacked in a vertical direction, a gate stack engaging with channel regions of the semiconductor fin, and source/drain (S/D) features disposed adjacent to the gate stack in S/D regions of the semiconductor fin. In the present embodiments, the gate stack includes a first portion disposed over the semiconductor layers and a second portion disposed between the semiconductor layers, where the first portion includes a work-function metal (WFM) layer and a metal fill layer disposed over the WFM layer and the second portion includes the WFM layer but is free of the metal fill layer.

The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.

Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a first transistor in a first area and a second transistor in a second area. The first transistor includes a first gate structure extending lengthwise along a first direction, and a first gate spacer, a second gate spacer, and a third gate spacer over sidewalls of the first gate structure. The second transistor includes a second gate structure extending lengthwise along the first direction, and the first gate spacer and the third gate spacer over sidewalls of the second gate structure. The first gate spacer, the second gate spacer and the third gate spacer are of different compositions and the third gate spacer is directly on the first gate spacer in the second area.

According to the present disclosure, hybrid fins positioned between two different epitaxial source/drain features are recessed to prevent conductive material from entering interior air gaps of the hybrid fins, thus, preventing short circuit between source/drain contacts and gate electrodes. Recessing the hybrid fins may be achieved by enlarging mask during semiconductor fin etch back, therefore, without increasing production cost.

A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked, the first and second semiconductor layers having different material compositions; forming a sacrificial gate structure over the fin structure; forming a gate spacer on sidewalls of the sacrificial gate structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure and the gate spacer, thereby forming an S/D trench; laterally etching the first semiconductor layers through the S/D trench, thereby forming recesses; selectively depositing an insulating layer on surfaces of the first and second semiconductor layers exposed in the recesses and the S/D trench, but not on sidewalls of the gate spacer; and growing an S/D epitaxial feature in the S/D trench, thereby trapping air gaps in the recesses.

A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.