A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.

A method of manufacturing a semiconductor structure is provided. The method includes providing a semiconductor substrate having an active region, forming a fin structure in the active region, and forming a conductive element on the body portion and the first tapered portion of the fin structure. The fin structure includes a body portion, and a first tapered portion protruding from an upper surface of the body portion.

An n-MOS transistor device and method for forming such a device are disclosed. The n-MOS transistor device comprises a semiconductor substrate with one or more replacement active regions formed above the substrate. The replacement active regions comprise a first III-V semiconductor material. A gate structure is formed above the replacement active regions. Source/Drain (S/D) recesses are formed in the replacement active region adjacent to the gate structure. Replacement S/D regions are formed in the S/D recesses and comprise a second III-V semiconductor material having a lattice constant that is smaller than the lattice constant of the first III-V semiconductor material. The smaller lattice constant of the second III-V material induces a uniaxial-strain on the channel formed from the first III-V material. The uniaxial strain in the channel improves carrier mobility in the n-MOS device.

Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.

Embodiments disclosed herein include transistor devices and methods of forming such transistor devices. In an embodiment a transistor comprises a substrate, and a fin that extends up from the substrate. In an embodiment, the fin comprises a source region, a drain region, and a channel region between the source region and the drain region. In an embodiment, the transistor further comprises and a cavity in the fin, where the cavity is below the channel region. In an embodiment, the transistor further comprises a gate stack over the fin.

A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate, wherein each fin includes a first sidewall and a second sidewall opposing each other. The method also includes forming a sacrificial layer over the fin. Further, the method also includes performing a first ion implantation process on the first sidewall and a top of the fin, and performing a second ion implantation process on the second sidewall and the top of the fin.

A device includes a gate isolation plug, which further includes a U-shaped layer having a bottom portion and two sidewall portions, and an inner region overlapping the bottom portion. The inner region contacts the two sidewall portions. A first transistor has a first gate stack, and a first end of the first gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. A second transistor has a second gate stack, and a second end of the second gate stack is in contact with both the inner region and the U-shaped layer of the gate isolation plug. The first gate stack and the second gate stack are on opposite sides of the gate isolation plug.

In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.

A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the channel region.