A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern.

A composite power element includes a substrate structure, an insulation layer, a dielectric layer, a MOSFET, and a Zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The Zener diode is formed in a circuit element formation region of the substrate structure, and includes a Zener diode doping structure that is formed in the substrate structure and is covered by the insulation layer. The Zener diode doping structure includes a first P-type doped region and a first N-type doped region that is formed on an inner side of the first P-type doped region. The Zener diode further includes a Zener diode metal structure that is formed on the dielectric layer and sequentially passes through the dielectric layer and the insulation layer to be electrically connected to the first P-type doped region and the first N-type doped region.

A semiconductor device includes a semiconductor layer that has a transistor structure including a p type source region, a p type drain region, an n type body region between the p type source region and the p type drain region, and a gate electrode facing the n type body region and a voltage-regulator diode that is disposed at the semiconductor layer and that has an n type portion connected to the p type source region and a p type portion connected to the gate electrode, in which the transistor structure and the voltage-regulator diode are unified into a single-chip configuration.

A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel stopper formed in an outer peripheral region of the semiconductor substrate, and an insulating film that covers a surface of the semiconductor substrate and that has a first contact hole by which the channel stopper is exposed. The semiconductor device further includes a first field plate, a second field plate, and an equipotential ring electrode. The first field plate is formed on the insulating film, and faces the semiconductor substrate between the channel stopper and the element region through the insulating film. The second field plate is embedded in the insulating film, and faces the semiconductor substrate between the first field plate and the channel stopper through the insulating film. The equipotential ring electrode is formed along an outer peripheral region of the semiconductor substrate. The equipotential ring electrode is connected to the channel stopper through the first contact hole, and is connected to the first field plate, and is connected to the second field plate through a second contact hole formed in the insulating film.

A semiconductor device according to the present invention includes a semiconductor layer, a gate trench defined in the semiconductor layer, a first insulating film arranged on the inner surface of the gate trench, a gate electrode arranged in the gate trench via the first insulating film, and a source layer, a body layer, and a drain layer arranged laterally to the gate trench, in which the first insulating film includes, at least at the bottom of the gate trench, a first portion and a second portion with a film elaborateness lower than that of the first portion from the inner surface of the gate trench in the film thickness direction.

In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed, wherein: the shielded gate structure comprises a first poly-silicon layer to serve as a shielded electrode and a second poly-silicon layer to serve as a gate electrode, and the ESD clamp diode formed between two protruding electrodes is also formed by the first poly-silicon layer. A mask specially used to define the ESD clamp diode portion is saved.

In an embodiment, a semiconductor die includes a transistor device that has a cell field and an edge termination region, a source pad arranged on the cell field, a gate pad laterally arranged laterally adjacent the cell field and in the edge termination region, a shielding region laterally surrounding the cell field, the shielding region including a non-depletable doped. The polysilicon ESD protection diode is arranged laterally between the gate pad and the source pad and vertically above at least a portion of the shielding region, and includes at least two separate sections that are electrically coupled in parallel between the gate pad and the source pad. The sections are laterally spaced apart by a gap situated at a corner of the gate pad.

An integrated device includes at least one MOS transistor having a plurality of cells. In each of one or more of the cells a disabling structure is provided. The disabling structure is configured to be in a non-conductive condition when the MOS transistor is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor and an intervention voltage of the disabling structure, or to be in a conductive condition otherwise. A system comprising at least one integrated device as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device is proposed.

A semiconductor device includes a semiconductor body having opposite first and second surfaces. The semiconductor device further includes a transistor structure in the semiconductor body and a source contact structure overlapping the transistor structure. The source contact structure is electrically connected to source regions of the transistor structure. A gate contact structure is further provided, which has a part separated from the source contact structure by a longitudinal gap within a lateral plane. Gate interconnecting structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and a gate electrode of the transistor structure. Electrostatic discharge protection structures bridge the longitudinal gap and are electrically coupled between the gate contact structure and the source contact structure. At least one of the gate interconnecting structures is between two of the electrostatic discharge protection structures along a length direction of the longitudinal gap.