A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.

A wide gap semiconductor device has: a first MOSFET region (M0) having a first gate electrode 10 and a first source region 30 provided in a first well region 20 made of a second conductivity type; a second MOSFET region (M1) provided below a gate pad 100 and having a second gate electrode 110 and a second source region 130 provided in a second well region 120 made of the second conductivity type; and a built-in diode region electrically connected to the second gate electrode 110. The second source region 130 of the second MOSFET region (M1) is electrically connected to the gate pad 100.

A method for improving breakdown voltage of a Laterally Diffused Metal Oxide Semiconductor (LDMOS) includes biasing a first well of a Field Effect Transistor (FET) to a first voltage. The first well is laterally separated from a second well. An isolation ring is charged to a second voltage in response to the first voltage exceeding a breakdown voltage of a diode connected between the isolation ring and the first well. The isolation ring laterally surrounds the FET and contacts a buried layer (BL) extending below the first well and the second well. A substrate is biased to a third voltage being less than or equal to the first voltage. The substrate laterally extends below the BL and contacts the BL.

A semiconductor device includes a first drive circuit and a bootstrap control circuit. When a voltage V.sub.B is equal to or smaller than a power supply voltage V.sub.CC, the boost control circuit turns on a MOSFET by controlling a gate signal input to a gate terminal, and a back gate control circuit makes a voltage applied to a back gate terminal smaller than the voltage V.sub.B.

A semiconductor device configures a protection element that protects a protection target element connected between a cathode electrode and an anode electrode when a parasitic transistor configured by a cathode region, a first conductivity type well layer, and a second conductivity type well is turned on and electrical continuity is established between the cathode electrode and the anode electrode. The semiconductor device includes a plurality of body regions in one cell of the protection element, and the plurality of body regions is brought in contact with the cathode electrode.

A semiconductor device includes a first drive circuit and a bootstrap control circuit. When a voltage V.sub.B is equal to or smaller than a power supply voltage V.sub.CC, the boost control circuit turns on a MOSFET by controlling a gate signal input to a gate terminal, and a back gate control circuit makes a voltage applied to a back gate terminal smaller than the voltage V.sub.B.

A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.

A structural body made of semiconductor material includes an active area housing a drain region, a body region and a source region within the body region. An electrical-isolation trench extends in the structural body to surround the active area. A first PN-junction and a second PN-junction are integrated in the structural body between the active area and the trench, respectively located on opposite sides of the active area. The first and the second PN-junctions form a first diode and a second diode, with each diode having a respective cathode electrically coupled to the drain region of the MOSFET device and a respective anode electrically coupled to the source region of the MOSFET device.

An electrostatic discharge (ESD) protection device includes a substrate, a first gate group and a second gate group on the substrate, a drain region and a fourth doped region respectively at two sides of the first gate group, a source region and the fourth doped region respectively at two sides of the second gate group, a first doped region in the substrate and surrounded by the drain region, and a second doped region in the substrate and surrounded by the fourth doped region. The drain region and the source region have a first conductivity type. The first doped region and the second doped region have a second conductivity type complementary to the first conductivity type. The drain region is electrically connected to an input/output pad. The source region is electrically connected to a ground pad. The first doped region and the second doped region are electrically connected to each other.

A transistor device includes a substrate a first transistor structure. The first transistor structure includes a first fin structure on the substrate. The first fin structure includes a first doped region, and a second fin structure on the substrate spaced apart from the first fin structure. The second fin structure includes a second doped region and a third doped region spaced apart from the second doped region. The transistor device includes a first electrode on the second fin structure and covering a first end of the second fin structure.