The invention provides a power device, which includes: an operation layer, including a top surface, a body region and a drift region, the body region and the drift region being connected in a lateral direction, to form a PN junction along a channel width direction between the body region and the drift region; a gate, formed on the top surface, and the PN junction is located under the gate; a source, formed in a portion of the operation layer between the body region and the top surface; a drain, formed in another portion of the operation layer between the drift region and the top surface; a first conduction portion, formed on the top surface for electrically connecting the source; a conduction layer, formed on the first conduction portion and electrically connected to the source via the first conduction portion; and a second conduction portion, formed on the top surface and between the conduction layer and the drift region in a thickness direction, for electrically connecting the drift region and the conduction layer, wherein a Schottky diode is formed by the second conduction portion and the drift region.

An embodiment of the invention shows a high-voltage MOS field-effect transistor connected in series with a Schottky diode. When the Schottky diode is forwardly biased, the high-voltage MOSFET can act as a switch and sustain a high drain-to-source voltage. When the Schottky diode is reversely biased, the Schottky diode can protect the integrate circuit where the high-voltage MOSFET is formed, because the integrate circuit might otherwise burn out due to an exceedingly-large reverse current.

The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.

The present disclosure provides a semiconductor device, including a substrate, a first dopant region in the substrate, wherein the first dopant is doped with a first conductivity type dopant, a first drift region at a top surface of the substrate, a first drain region adjacent to the first drift region, a second drain region, wherein an upper portion of the first dopant region is between the first drain region and the second drain region, and a first conductive layer connecting the first drain region, the second drain region, and a top surface of the upper portion of the first dopant region, wherein a Schottky barrier interface is formed between the top surface of the upper portion of the first dopant region and the first conductive layer.