H01L2224/05169

DRY ETCH PROCESS LANDING ON METAL OXIDE ETCH STOP LAYER OVER METAL LAYER AND STRUCTURE FORMED THEREBY

A microelectronic device includes a metal layer on a first dielectric layer. An etch stop layer is disposed over the metal layer and on the dielectric layer directly adjacent to the metal layer. The etch stop layer includes a metal oxide, and is less than 10 nanometers thick. A second dielectric layer is disposed over the etch stop layer. The second dielectric layer is removed from an etched region which extends down to the etch stop layer. The etched region extends at least partially over the metal layer. In one version of the microelectronic device, the etch stop layer may extend over the metal layer in the etched region. In another version, the etch stop layer may be removed in the etched region. The microelectronic device is formed by etching the second dielectric layer using a plasma etch process, stopping on the etch stop layer.

Method for Producing a Connection Between Component Parts, and Component Made of Component Parts

A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.

Method for Producing a Connection Between Component Parts, and Component Made of Component Parts

A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.

Bump bond structure for enhanced electromigration performance

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

Bump bond structure for enhanced electromigration performance

A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

Conductive paste for bonding
10756047 · 2020-08-25 · ·

The present invention relates to a conductive paste for bonding that comprises a metal powder and a solvent, wherein the metal powder comprises a first metal powder having a particle diameter (D50) of 10 to 150 nm and a second metal powder having a particle diameter (D50) of 151 to 500 nm. The paste is useful for manufacturing an electronic device comprising a substrate with an electrically conductive layer and an electrical or electronic component, which are reliably bonded together using the paste.

Conductive paste for bonding
10756047 · 2020-08-25 · ·

The present invention relates to a conductive paste for bonding that comprises a metal powder and a solvent, wherein the metal powder comprises a first metal powder having a particle diameter (D50) of 10 to 150 nm and a second metal powder having a particle diameter (D50) of 151 to 500 nm. The paste is useful for manufacturing an electronic device comprising a substrate with an electrically conductive layer and an electrical or electronic component, which are reliably bonded together using the paste.

Light-emitting diode and application therefor

A light emitting diode apparatus includes a substrate, a first conductive type semiconductor layer, a second conductive type semiconductor layer, a mesa, a lower insulating layer, a first pad and a second pad. The substrate has a first surface and a second surface opposite to the first surface. The first conductivity type semiconductor layer is disposed on the first surface of the substrate. The mesa is disposed on the first conductive semiconductor layer and has an active layer and the second conductive semiconductor layer. A peripheral edge of the first conductive semiconductor layer is exposed. The lower insulating layer covers the mesa and the first conductive semiconductor layer and has a plurality of first openings exposing the first conductive semiconductor layer along a peripheral edge of the substrate.