A method of removing a substrate, comprising: forming a growth restrict mask with a plurality of striped opening areas directly or indirectly upon a GaN-based substrate; and growing a plurality of semiconductor layers upon the GaN-based substrate using the growth restrict mask, such that the growth extends in a direction parallel to the striped opening areas of the growth restrict mask, and growth is stopped before the semiconductor layers coalesce, thereby resulting in island-like semiconductor layers. A device is processed for each of the island-like semiconductor layers. Etching is performed until at least a part of the growth restrict mask is exposed. The devices are then bonded to a support substrate. The GaN-based substrate is removed from the devices by a wet etching technique that at least partially dissolves the growth restrict mask. The GaN substrate that is removed then can be recycled.

A semiconductor package is provided. The semiconductor package includes a first die having a plurality of first metal pads at a first bonding side and a second die over the first die, having a plurality of second metal pads at a second bonding side facing the first bonding side. Each of the first metal pads corresponds to each of the second metal pads with a pitch no greater than about 10 ?m. The semiconductor package further includes a first dielectric layer surrounding and in contact with a sidewall of the first metal pads and a second dielectric layer surrounding and in contact with a sidewall of the second metal pads. A method for manufacturing a semiconductor package is also provided.

Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.

Airtightness of a hollow portion is maintained, and yield and durability are improved. A semiconductor device 1 includes a device substrate 2, a semiconductor circuit 3, a sealing frame 7, a cap substrate 8, via portions 10, electrodes 11, 12 and 13, and a bump portion 14 or the like. A hollow portion 9 in which the semiconductor circuit 3 is housed in an airtight state is provided between the device substrate 2 and the cap substrate 8. The bump portion 14 connects all the via portions 10 and the cap substrate 8. Thus, the via portions 10 can be reinforced using the bump portion 14A.

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

Described are concepts, systems, circuits and techniques related to shielded through via structures and methods for fabricating such shielded through via structures. The described shielded through via structures and techniques allow for assembly of multi-layer semiconductor structures including one or more superconducting semiconductor structures (or integrated circuits).

Described are concepts, systems, circuits and techniques related to shielded through via structures and methods for fabricating such shielded through via structures. The described shielded through via structures and techniques allow for assembly of multi-layer semiconductor structures including one or more superconducting semiconductor structures (or integrated circuits).

An UBM electrode structure body for a radiation detector and a radiation detector arranged with the UBM electrode structure body are provided for suppressing peeling and having high electrode adhesion. In addition, a manufacturing method of an UBM electrode structure body for a radiation detector and a manufacturing method of a radiation detector using the UBM electrode structure body are provided in which peeling does not occur during UBM structure formation, a solder bonding process or bonding of a signal line to a Pt layer. The UBM electrode structure body for a radiation detector of the present invention is arranged with a CdTe substrate or CdZnTe substrate and a Pt electrode layer arranged on the CdTe substrate or CdZnTe substrate, adhesion of the Pt electrode layer with respect to the CdTe substrate or the CdZnTe substrate being 0.5 N/cm or more.

A semiconductor light-emitting device includes a light-emitting structure including a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked. A connection electrode is positioned above the light-emitting structure. The connection electrode includes a connection metal layer electrically connected to at least one of the first and second semiconductor layers. A UBM pattern is on the connection electrode. A connection terminal is on the UBM pattern. The connection metal layer includes a first metal element. A heat conductivity of the first metal element is higher than that of gold (Au). The connection terminal includes a second metal element. A first reactivity of the first metal element with the second metal element is lower than a second reactivity of gold (Au) with the second metal element.