H01L2224/05169

Multiple bond via arrays of different wire heights on a same substrate
20180301436 · 2018-10-18 · ·

Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (first wires) extend from a surface of the substrate. Second wire bond wires (second wires) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.

Semiconductor Device with Metallization Structure and Method for Manufacturing Thereof
20180301338 · 2018-10-18 ·

A semiconductor device includes a semiconductor substrate with a first side and a second side, and at least one doping region formed at the first side of the semiconductor substrate. The semiconductor device further includes a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region, and a second metallization structure at the second side of the semiconductor substrate. The second metallization structure forms a silicide interface region with the semiconductor substrate and a non-silicide interface region with the semiconductor substrate.

Semiconductor Device with Metallization Structure and Method for Manufacturing Thereof
20180301338 · 2018-10-18 ·

A semiconductor device includes a semiconductor substrate with a first side and a second side, and at least one doping region formed at the first side of the semiconductor substrate. The semiconductor device further includes a first metallization structure at the first side of the semiconductor substrate and on and in contact with the at least one doping region, and a second metallization structure at the second side of the semiconductor substrate. The second metallization structure forms a silicide interface region with the semiconductor substrate and a non-silicide interface region with the semiconductor substrate.

LIGHT EMITTING DIODE MODULE FOR SURFACE MOUNT TECHNOLOGY AND METHOD OF MANUFACTURING THE SAME

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

LIGHT EMITTING DIODE MODULE FOR SURFACE MOUNT TECHNOLOGY AND METHOD OF MANUFACTURING THE SAME

An LED is provided to include: a first conductive type semiconductor layer; an active layer positioned over the first conductive type semiconductor layer; a second conductive type semiconductor layer positioned over the active layer; and a defect blocking layer comprising a masking region to cover at least a part of the top surface of the second conductive semiconductor layer and an opening region to partially expose the top surface of the second conductive type semiconductor layer, wherein the active layer and the second conductive type semiconductor layer are disposed to expose a part of the first conductive type semiconductor layer, and wherein the defect blocking layer comprises a first region and a second region surrounding the first region, and a ratio of the area of the opening region to the area of the masking region in the first region is different from a ratio of the area of the opening region to the area of the masking region in the second region.

Semiconductor device

A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an electrode pad disposed on the first protective film; a second protective film disposed to cover and be in contact with the electrode pad and the first adhesive layer; and a first opening formed in part of the second protective film such that the upper surface of the electrode pad is exposed, wherein in a plan view, the first adhesive layer includes a first projection projecting from the electrode pad radially in a direction of the periphery of the electrode pad and continuously surrounding the periphery of the electrode pad; and the second protective film is continuously to cover and contact part of the upper and side surfaces of the electrode pad, the upper and side surfaces of first projection, and the first protective film.

System and method for dual-region singulation

A semiconductor die includes a semiconductor circuit disposed within or over a substrate. A conductive contact pad is disposed over the substrate outside the semiconductor circuit. A floating electrical path ends at a singulated edge of the die. The electrical path is electrically coupled to the conductive contact pad.

Semiconductor device and method to minimize stress on stack via
12080600 · 2024-09-03 · ·

A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.

HEAT DISSIPATION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
20240321679 · 2024-09-26 · ·

A heat dissipation structure may include a heat dissipation chamber including a lower wall, an upper wall on the lower wall, and a plurality of sidewalls extending between the lower wall and the upper wall, the heat dissipation chamber providing an inner space for a working fluid to flow therein; and a wick structure on an inner surface of the heat dissipation chamber. The wick structure may be configured to guide the working fluid in a liquid state. The heat dissipation chamber may be configured to change its shape according to a temperature.

Semiconductor chip with redundant thru-silicon-vias

A semiconductor chip with conductive vias and a method of manufacturing the same are disclosed. The method includes forming a first plurality of conductive vias in a layer of a first semiconductor chip The first plurality of conductive vias includes first ends and second ends. A first conductor pad is formed in ohmic contact with the first ends of the first plurality of conductive vias.