A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

A method of manufacturing a semiconductor package including coating a flux on a connection pad provided on a first surface of a substrate, the flux including carbon nanotubes (CNTs), placing a solder ball on the connection pad coated with the flux, forming a solder layer attached to the connection pad from the solder ball through a reflow process, and mounting a semiconductor chip on the substrate such that the solder layer faces a connection pad in the semiconductor chip may be provided.

An interposer includes element mounting sections and terminal sections directly and partly formed on a surface of an aluminum film having the predetermined pattern. Each of the element mounting sections and the terminal sections has a laminated structure of an Ni film, an Pd film and an Au film. The interposer is formed with an AuSn layer on a predetermined region of a surface of each Au film in the element mounting sections. The interposer includes a protective film having optical permeability that directly covers a region of the surface of the aluminum film, which is out of contact with the element mounting sections and the terminal sections.

An interposer includes element mounting sections and terminal sections directly and partly formed on a surface of an aluminum film having the predetermined pattern. Each of the element mounting sections and the terminal sections has a laminated structure of an Ni film, an Pd film and an Au film. The interposer is formed with an AuSn layer on a predetermined region of a surface of each Au film in the element mounting sections. The interposer includes a protective film having optical permeability that directly covers a region of the surface of the aluminum film, which is out of contact with the element mounting sections and the terminal sections.

A sensor device for use in harsh media, comprising a silicon die comprises a lowly doped region, and a contact layer, contacting the silicon die. The contact layer comprises a refractory metal and an ohmic contact to the silicon die via a silicide of the refractory metal. A noble metal layer is provided over the contact layer such that the contact layer is completely covered by the noble metal layer. The noble metal layer comprises palladium, platinum or a metal alloy of palladium and/or platinum. The noble metal layer is patterned to form an interconnect structure and a contact connecting via the contact layer to the ohmic contact. The noble metal layer is adapted for providing a shield to prevent modulation of the lowly doped region by surface charges. The noble metal layer may advantageously protect the contact layer against harsh media in an external environment of the sensor device.

A sensor device for use in harsh media, comprising a silicon die comprises a lowly doped region, and a contact layer, contacting the silicon die. The contact layer comprises a refractory metal and an ohmic contact to the silicon die via a silicide of the refractory metal. A noble metal layer is provided over the contact layer such that the contact layer is completely covered by the noble metal layer. The noble metal layer comprises palladium, platinum or a metal alloy of palladium and/or platinum. The noble metal layer is patterned to form an interconnect structure and a contact connecting via the contact layer to the ohmic contact. The noble metal layer is adapted for providing a shield to prevent modulation of the lowly doped region by surface charges. The noble metal layer may advantageously protect the contact layer against harsh media in an external environment of the sensor device.

A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

An SiC semiconductor device includes an SiC chip having a first main surface at one side and a second main surface at another side, a first main surface electrode including a first Al layer and formed on the first main surface, a pad electrode formed on the first main surface electrode and to be connected to a lead wire, and a second main surface electrode including a second Al layer and formed on the second main surface.