A semiconductor structure includes heterojunction bipolar transistors arranged in parallel and disposed on a substrate. The semiconductor structure also includes a landing structure disposed at the edge of the HBTs on the substrate. The semiconductor structure also includes wiring disposed on the HBTs and connected to the landing structure. The semiconductor structure also includes an insulating layer disposed on the landing structure and having a via. The semiconductor structure also includes a bump disposed on the top surface of the insulating layer and connected to the wiring through the via. The sidewall of the landing structure has a recess in a top view.

A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.

A semiconductor component includes a semiconductor substrate, conductive vias in the substrate having terminal portions, a polymer layer on the substrate and back side conductors formed by the terminal portions of the conductive vias embedded in the polymer layer. A stacked semiconductor component includes a plurality of components having aligned conductive vias in electrical communication with one another.

An example system includes a plating apparatus and processing circuitry. The plating apparatus may be configured to plate a coating including a plating composition on an electrical contact of a circuit substrate. The processing circuitry may be further configured to cause the plating apparatus to plate a first layer of the coating on the electrical contact of the circuit substrate using a first current density. The processing circuitry may be further configured to plate a second layer of the coating on the first layer using a second current density that is higher than the first current density. The second layer may include a nodular deposit including the plating composition.

In some embodiments, laser devices having contact pads are formed. The laser diodes are formed from a doped semiconductive material. The contact pads and semiconductive material share an ohmic junction. Underbump metallurgies are formed on the contact pads. Conductive connectors are electrically coupled to the laser devices. The underbump metallurgies help prevent metal inter-diffusion between the contact pads and conductive connectors. As such, when reflowing the conductive connectors, the junction of the contact pads and semiconductive material may retain its ohmic properties.

In some embodiments, laser devices having contact pads are formed. The laser diodes are formed from a doped semiconductive material. The contact pads and semiconductive material share an ohmic junction. Underbump metallurgies are formed on the contact pads. Conductive connectors are electrically coupled to the laser devices. The underbump metallurgies help prevent metal inter-diffusion between the contact pads and conductive connectors. As such, when reflowing the conductive connectors, the junction of the contact pads and semiconductive material may retain its ohmic properties.

A semiconductor device assembly, comprising a first semiconductor device including a first substrate with a frontside surface, a plurality of solder bumps located on the frontside surface of the first substrate, and a first polymer layer on the frontside surface. The semiconductor device assembly also comprises a second semiconductor device including a second substrate with a backside surface, a plurality of TSVs protruding from the backside surface of the second substrate, and a second polymer layer on the backside surface of the first substrate, the second polymer layer having a plurality of openings corresponding to the plurality of TSVs. The first and second semiconductor devices are bonded such that the first polymer layer contacts the second polymer layer and each of the plurality of solder bumps extends into a corresponding one of the plurality of openings and contacts a corresponding one of the plurality of TSVs.

A semiconductor chip includes a chip body, an external electrode, and a buffer electrode formed between the chip body and the external electrode. The buffer electrode includes a tensile stress layer, and the tensile stress layer is formed by alternately stacking multiple metal layers with a large thermal expansion coefficient and multiple metal layers with a small thermal expansion coefficient, to offset at least part of a compressive stress in an epitaxial layer of the chip body. The buffer electrode has a tensile stress system formed by alternately stacking metal layers with a large thermal expansion coefficient and metal layers with a small thermal expansion coefficient, which can offset at least part of the compressive stress within the epitaxial layer of the chip body, thereby reducing the warping degree of the thinned wafer and improving the chip yield.

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.

Disclosed is a semiconductor device including a conductive pattern on a substrate, a passivation layer on the substrate and including an opening that partially exposes the conductive pattern, and a pad structure in the opening of the passivation layer and connected to the conductive pattern. The pad structure includes a first metal layer that fills the opening of the passivation layer and has a width greater than that of the opening, and a second metal layer on the first metal layer. The first metal layer has a first thickness at an outer wall of the first metal layer, a second thickness on a top surface of the passivation layer, and a third thickness on a top surface of the conductive pattern. The second thickness is greater than the first thickness, and the third thickness is greater than the second thickness.