A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

A semiconductor device includes a semiconductor chip having a first face and a second face on an opposite side to the first face, and including semiconductor elements arranged on the first face. Columnar electrodes are arranged above the first face, and electrically connected to any of the semiconductor elements. A first member is located around the columnar electrodes above the first face. An insulant covers the columnar electrodes and the first member. The first member is harder than the columnar electrodes and the insulant. The first member and the columnar electrodes are exposed from a surface of the insulant.

The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 510.sup.6/ C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

An object of the present invention is to stabilize and strengthen the strength of a bonding part between a metal electrode on a semiconductor chip and metal wiring connected thereto using a simple structure. Provided is a semiconductor device including a metal layer 130 on a surface of a metal electrode 120 formed on a semiconductor chip 110, the metal layer 130 consisting of a metal or an alloy different from a constituent metal of the metal electrode 120, metal wiring 140 is connected to the metal layer 130 via a bonding part 150, wherein the constituent metal of the metal layer 130 is a metal or an alloy different from the constituent metal of the metal electrode 120, and the bonding part 150 has an alloy region harder than the metal wiring 140.

An object of the present invention is to stabilize and strengthen the strength of a bonding part between a metal electrode on a semiconductor chip and metal wiring connected thereto using a simple structure. Provided is a semiconductor device including a metal layer 130 on a surface of a metal electrode 120 formed on a semiconductor chip 110, the metal layer 130 consisting of a metal or an alloy different from a constituent metal of the metal electrode 120, metal wiring 140 is connected to the metal layer 130 via a bonding part 150, wherein the constituent metal of the metal layer 130 is a metal or an alloy different from the constituent metal of the metal electrode 120, and the bonding part 150 has an alloy region harder than the metal wiring 140.

According to an embodiment, a semiconductor device includes a silicon substrate, a semiconductor layer, and a lower layer. The semiconductor layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

According to an embodiment, a semiconductor device includes a silicon substrate, a semiconductor layer, and a lower layer. The semiconductor layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

The present disclosure provides a semiconductor packaging method and a semiconductor package device. The method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface; soldering pads disposed at the front surface of a chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate. A first end of the metal part away from a corresponding soldering pad is in coplanar with the transparent protective layer; and the first end of the metal part is not covered by the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part to electrically connect the chip with the circuit board.

The present disclosure provides a semiconductor packaging method and a semiconductor package device. The method includes providing a chip, where the chip includes a chip substrate having a front surface and a back surface; soldering pads disposed at the front surface of a chip substrate surrounding the photosensitive region; a metal part formed on a side of each soldering pad facing away from the chip substrate; and a transparent protective layer formed on the front surface of the chip substrate. A first end of the metal part away from a corresponding soldering pad is in coplanar with the transparent protective layer; and the first end of the metal part is not covered by the transparent protective layer. The method further includes electrically connecting the first end of the metal part to a circuit board using a conductive connection part to electrically connect the chip with the circuit board.

A method for manufacturing a package includes positioning a copper layer above a die. A zinc layer is positioned on the copper layer. The zinc and copper layers are then heated to produce a brass layer, the brass layer abutting the copper layer. Further, a polymer layer is positioned abutting the brass layer.