A bonding pad for an integrated circuit is formed by a stack of bonding pad layers. A lower bonding pad layer is supported by a bonding pad support layer. A passivation layer extends over the lower bonding pad layer and includes a passivation opening at a portion of an upper surface of the lower bonding pad layer. An upper bonding pad layer rests on said passivation layer and in the passivation opening in contact with the lower bonding pad layer.

A light-emitting element including: a first semiconductor layer doped with a first type of dopant; a second semiconductor layer doped with a second type of dopant that is different from the first type of dopant; and an active layer between the first semiconductor layer and the second semiconductor layer, wherein a length of the light-emitting element measured in a first direction, which may be a direction in which the first semiconductor layer, the active layer, and the second semiconductor layer may be arranged, may be shorter than the width measured in a second direction that is perpendicular to the first direction.

A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element.

A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element.

A method for forming a semiconductor device is provided. The method includes the following steps: providing a semiconductor substrate; forming a pad layer on the semiconductor substrate; forming a first passivation layer on the pad layer; forming a second passivation layer on the first passivation layer, wherein the second passivation layer comprises polycrystalline silicon; forming an oxide layer on the second passivation layer; forming a nitride layer on the oxide layer; removing a portion of the oxide layer and a portion of the nitride layer to expose a portion of the second passivation layer; removing the portion of the second passivation layer that has been exposed to expose a portion of the first passivation layer; and removing the portion of the first passivation layer that has been exposed to expose a portion of the pad layer.

A method for forming a semiconductor device is provided. The method includes the following steps: providing a semiconductor substrate; forming a pad layer on the semiconductor substrate; forming a first passivation layer on the pad layer; forming a second passivation layer on the first passivation layer, wherein the second passivation layer comprises polycrystalline silicon; forming an oxide layer on the second passivation layer; forming a nitride layer on the oxide layer; removing a portion of the oxide layer and a portion of the nitride layer to expose a portion of the second passivation layer; removing the portion of the second passivation layer that has been exposed to expose a portion of the first passivation layer; and removing the portion of the first passivation layer that has been exposed to expose a portion of the pad layer.

A semiconductor device with a connection pad in a substrate, the connection pad having an exposed surface made of a metallic material that diffuses less readily into a dielectric layer than does a metal of a wiring layer connected thereto.

A semiconductor device includes a substrate that includes an opening extending through a thickness of the substrate, a frame that includes an integrated circuit (IC) die pad in the opening and a plurality of arms extending outwardly from the IC die pad, an IC mounted on the IC die pad, a plurality of bonding elements electrically coupling the substrate with the IC without the frame being an intermediary coupling element, and an encapsulant surrounding the IC, the plurality of bonding elements, and the plurality of arms. The substrate has a first major surface and a second major surface. Each arm is devoid of a contact pad. Each arm has a distal end coupled to the first major surface of the substrate, and each arm has a proximal end disposed over the first major surface of the substrate.

A semiconductor device includes a substrate that includes an opening extending through a thickness of the substrate, a frame that includes an integrated circuit (IC) die pad in the opening and a plurality of arms extending outwardly from the IC die pad, an IC mounted on the IC die pad, a plurality of bonding elements electrically coupling the substrate with the IC without the frame being an intermediary coupling element, and an encapsulant surrounding the IC, the plurality of bonding elements, and the plurality of arms. The substrate has a first major surface and a second major surface. Each arm is devoid of a contact pad. Each arm has a distal end coupled to the first major surface of the substrate, and each arm has a proximal end disposed over the first major surface of the substrate.

A method of forming a sandwich passivation layer (405) on a semiconductor device (400) comprising a bond pad (404) is provided. The method comprises forming a first layer (406) over a surface of the semiconductor device (400), removing a part of the first layer (406) to expose a surface of the bond pad (404), forming a second layer (407) over the first layer (406) and the surface of the bond pad (404), and forming a third layer (408) over the second layer (407), wherein the surface of the bond pad (404) is not in contact with the first layer (406) or third layer (408).