A semiconductor structure includes a substrate, a passivation layer on the substrate, a post-passivation interconnect (PPI) structure on the passivation layer, and a polymer layer covering the PPI structure and the passivation layer. The PPI structure includes a step structure disposed on the passivation layer and around a lower edge of the PPI structure.

A semiconductor structure includes a substrate, a passivation layer on the substrate, a post-passivation interconnect (PPI) structure on the passivation layer, and a polymer layer covering the PPI structure and the passivation layer. The PPI structure includes a step structure disposed on the passivation layer and around a lower edge of the PPI structure.

A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.

A semiconductor device includes: a substrate including a semiconductor chip region, a guard ring region adjacent to the semiconductor chip region, and an edge region adjacent to the guard ring region; a first interlayer insulating layer disposed on the substrate; a wiring structure disposed inside the first interlayer insulating layer and in the guard ring region, wherein the wiring structure includes a first wiring layer and a second wiring layer disposed above the first wiring layer; and a trench configured to expose at least a part of the first interlayer insulating, layer in the edge region, wherein the trench includes a first bottom surface and a second bottom surface formed at a level different from that of the first bottom surface, wherein the first bottom surface is formed between the wiring structure and the second bottom surface, and the second bottom surface is formed adjacent to the first bottom surface.

A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.

A method for fabricating a semiconductor structure is provided. The method includes forming a semiconductor chip; providing a printed circuit board; and forming an adhesive layer between a connection surface of the semiconductor chip and the printed circuit board to bond the semiconductor chip with the printed circuit board. The semiconductor chip includes a plurality of cutting tracks intersected with each other to enclose an area having corner regions. The connection surface of the semiconductor chip includes a plurality of conductive bumps and a plurality of first openings are formed in each of the corner regions.

A light emitting apparatus includes: a mount substrate; at least one light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the at least one light emitting device via at least one adhesive material layer, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the light emitting devices, and wherein a lateral surface of the light transparent member is located laterally inward of a lateral surface of the at least one light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.

A light emitting apparatus includes: a mount substrate; at least one light emitting device mounted on the mount substrate; a light transparent member, wherein a lower surface of the light transparent member is attached to an upper surface of the at least one light emitting device via at least one adhesive material layer, wherein the light transparent member has a plate shape and is positioned to receive incident light emitted from the light emitting devices, and wherein a lateral surface of the light transparent member is located laterally inward of a lateral surface of the at least one light emitting device; and a covering member that contains a light reflective material and covers at least the lateral surface of the light transparent member.

A light emitting device module includes a substrate, a plurality of light emitting devices mounted on the substrate, an adhesive layer interposed between the substrate and the light emitting device; and bonding wires electrically connecting the plurality of light emitting devices. The substrate includes an outer electrode in at least a partial region, and the adhesive layer has a non-conductive material.