Provided are a display panel and a display device. A peripheral circuit region is provided with a first pad group, a second pad group and multiple first signal lines. The first pad group includes a plurality of first pads, and the second pad group includes a plurality of second pads. An end of each of the plurality of the first signal lines adjacent to the first side is electrically connected to a respective one of the plurality of first pads, and an end of each of the plurality of the first signal lines adjacent to the second side is electrically connected to a respective one of the plurality of second pads.

A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes a base substrate, a sub-pixel unit, a data line, a scan line, a plurality of test contact pads, a first peripheral-zone insulating layer and an auxiliary electrode layer. The base substrate includes a display zone and a peripheral zone, the peripheral zone including a test bonding zone. Each of the plurality of the test contact pads includes a first test-contact-pad metal layer and a second test-contact-pad metal layer, wherein the second test-contact-pad metal layer covers the first test-contact-pad metal layer and contacts the first test-contact-pad metal layer in at least portion of a periphery of the first test-contact-pad metal layer. The auxiliary electrode layer includes a plurality of first relay electrode patterns located within the test bonding zone and a plurality of auxiliary electrodes located within the display zone.

A semiconductor device according to one embodiment includes: a semiconductor chip having a transistor and a drain pad provided on a board; a capacitor having an upper electrode and a lower electrode interposing a dielectric; a pad; and an empty pad provided on the board of the semiconductor chip. The semiconductor device further includes: a first wire connecting the pad and the drain pad of the semiconductor chip to each other; a second wire connecting the empty pad and the upper electrode of the capacitor to each other; and a third wire connecting the pad and the empty pad to each other.

A display apparatus includes a printed circuit board including first to fourth output pad regions and a flexible circuit board having a first end connected to a display panel and a second end connected to the printed circuit board. The first output pad region includes a 1.sup.st-1.sup.st output pad group and a 1.sup.st-2.sup.nd output pad group, the second output pad region includes a 2.sup.nd-1.sup.st output pad group and a 2.sup.nd-2.sup.nd output pad group, the fourth output pad region includes a 4.sup.th- 1.sup.st output pad group and a 4.sup.th-2.sup.nd output pad group, and the printed circuit board includes a first input terminal electrically connected to the 1.sup.st-1.sup.st output pad group, a second input terminal electrically connected to the 2.sup.nd-2.sup.nd output pad group, a third input terminal electrically connected to the first input terminal, and a fourth input terminal electrically connected to the 4.sup.th-2.sup.nd output pad group.

A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.

A display substrate and a preparing method thereof, and a display apparatus are provided. The display substrate includes a display region and a peripheral region, wherein the peripheral region includes a circuit board pin region and a test pin region which are located on at least one side of the display region. The display substrate further includes: a plurality of sub-pixels, and a first power supply line electrically connected with the plurality of sub-pixels; at least one first bonding power supply pin, located in the circuit board pin region, electrically connected with the first power supply line, and configured to transmit a first power supply signal to the plurality of sub-pixels in a display stage; a second power supply line, located in the peripheral region and surrounding the display region.

A device transfer substrate includes a plurality of recesses, wherein each of the plurality of recesses includes a first region having a shape of a first figure, a second region having a shape of a second figure, and an overlapping region formed as a portion of the first region partially overlaps a portion of the second region, wherein a maximum width of the overlapping region in a direction intersecting with a straight line passing through a center of the first figure and a center of the second figure is less than a diameter or a diagonal length of the first figure and less than a diameter or a diagonal length of the second figure.

A device transfer substrate includes a plurality of recesses, wherein each of the plurality of recesses includes a first region having a shape of a first figure, a second region having a shape of a second figure, and an overlapping region formed as a portion of the first region partially overlaps a portion of the second region, wherein a maximum width of the overlapping region in a direction intersecting with a straight line passing through a center of the first figure and a center of the second figure is less than a diameter or a diagonal length of the first figure and less than a diameter or a diagonal length of the second figure.

A package structure includes at least two semiconductor structures that are stacked onto one another. The first surface of one semiconductor structure of the at least two semiconductor structures that are stacked onto one another directly faces toward the second surface of another semiconductor structure of the at least two semiconductor structures which is adjacent to said one semiconductor structure; the first metal layer of said one semiconductor structure is in contact with and bonded to the third metal layer of said another semiconductor structure; and the second metal layer of said one semiconductor structure is in contact with and bonded to the fourth metal layer of said another semiconductor structure.