A package structure is provided. The package structure includes a first semiconductor package and a second semiconductor package connected to the first semiconductor package. The first semiconductor package includes an integrated circuit. The integrated circuit includes a first semiconductor die and a plurality of second semiconductor dies, the plurality of second semiconductor dies are stacked on the first semiconductor die, wherein at least one of orthogonal projections of the plurality of second semiconductor dies is partially overlapped an orthogonal projection of the first semiconductor die. The integrated circuit further includes through vias formed aside the first semiconductor and arranged in a non-overlapped region of the at least one of the orthogonal projections of the plurality of second semiconductor dies with the orthogonal projection of the first semiconductor die. A manufacturing method of a package structure is also provided.

First and second contacts are formed on first and second wafers from disparate first and second conductive materials, at least one of which is subject to surface oxidation when exposed to air. A layer of oxide-inhibiting material is disposed over a bonding surface of the first contact and the first and second wafers are positioned relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material. Thereafter, the first and second contacts and the layer of oxide-inhibiting material are heated to a temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond.

A method of making a micro-module structure comprises providing a substrate, the substrate having a substrate surface and comprising a substrate post protruding from the substrate surface. A component is disposed on the substrate post, the component having a component top side and a component bottom side opposite the component top side, the component bottom side disposed on the substrate post. The component extends over at least one edge of the substrate post. One or more component electrodes are disposed on the component.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure and a second semiconductor bonded with the first semiconductor structure. The first semiconductor structure includes an array of NAND memory strings, a semiconductor layer in contact with source ends of the array of NAND memory strings, an insulating layer in contact with the semiconductor layer, and a contact structure in the insulating layer. The insulating layer electrically insulates the contact structure from the semiconductor layer. The second semiconductor structure includes a transistor.

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

A display device includes a substrate, a plurality of pixel electrodes on the substrate and spaced apart from each other, a plurality of light-emitting elements on the plurality of pixel electrodes, respectively, and a common electrode layer on the plurality of light-emitting elements and to which a common voltage is applied. The plurality of light-emitting elements include a first light-emitting element that is configured to emit first light according to a first driving current and a second light-emitting element that is configured to emit second light according to a second driving current. An active layer of the first light-emitting element is the same as an active layer of the second light-emitting element.

In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

A method includes bonding a first wafer to a second wafer, and performing a trimming process on the first wafer. An edge portion of the first wafer is removed. After the trimming process, the first wafer has a first sidewall laterally recessed from a second sidewall of the second wafer. A protection layer is deposited and contacting a sidewall of the first wafer, which deposition process includes depositing a non-oxygen-containing material in contact with the first sidewall. The method further includes removing a horizontal portion of the protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.

Embodiments disclosed herein include semiconductor devices. In one embodiment, a die comprises a substrate, where the substrate comprises a semiconductor material. In an embodiment, a backend layer is over the substrate, where the backend layer comprises conductive routing. In an embodiment, the die further comprises a protrusion extending out from an edge of the substrate and the backend layer. In an embodiment, a fiducial is on a surface of the protrusion.

A semiconductor device includes a first die, the first die including a first dielectric layer and a plurality of first bond pads formed within apertures in the first dielectric layer, and a second die bonded to the first die, the second die including a second dielectric layer and a plurality of second bond pads protruding from the second dielectric layer. The first die is bonded to the second die such that the plurality of second bond pads protrude into the apertures in the first dielectric layer to establish respective metallurgical bonds with the plurality of first bond pads. A reduction in the distance between the respective bond pads of the dies results in a lower temperature for establishing a hybrid bond.