In some aspects, the disclosed technology provides microelectronic devices which can effectively dissipate heat and manage hot spot. In some embodiments, a disclosed microelectronic device may include a substrate having a thickness in a first direction and at least one thermoelectric unit disposed in or on the substrate. The thermoelectric unit may be configured to transfer heat along a second lateral direction orthogonal to the first direction.

A fan-out wafer-level package comprising at least one integrated circuit, an internal heat spreader thermally connected to the integrated circuit either directly or via an interface layer having a thickness in sub-μm range preferably in the range of 20 nm to 500 nm, wherein the internal heat spreader is embedded in the fan-out wafer-level package.

A semiconductor device includes: a semiconductor element; a heat radiator body having a housing recess wherein a bottom surface of the housing recess is thermally connected to the upper surface of the semiconductor element; a heat sink which is thermally connected to an upper surface of the heat radiator body through adhesive agent; a sealing resin which covers the lower surface and a side surface of the heat radiator body, an inner side surface of the housing recess, and the lower surface and a side surface of the semiconductor element; and a wiring structure body formed on a lower surface of the sealing resin. The sealing resin includes a covering portion having an upper surface which is substantially flush with the bottom surface of the housing recess and covering the side surface of the heat radiator body. The adhesive agent contacts the side surface of the heat radiator body.

An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

A semiconductor package structure is provided. The semiconductor package structure includes a substrate, a semiconductor die and a frame. The semiconductor die is disposed over the substrate. The frame is disposed over the substrate, wherein the frame is adjacent to the semiconductor die, and the upper surface of the frame is lower than the upper surface of the semiconductor die.

A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive vertical connection structure provided separately from the clip and electrically connecting the chip carrier with the clip.

A method of making an integrated circuit package includes: (a) forcing a circuit layered structure that includes a metal substrate and a circuit pattern, the metal substrate having opposite first and second surfaces, the circuit pattern including at least two spaced apart die contacts that protrude from the first surface of the metal substrate, the metal substrate directly interconnecting the die contacts; (b) bonding first and second terminal contacts of an electronic die to the die contacts, respectively; and (c) forming an insulator layer on the first surface of the metal substrate to encapsulate the die and the die contacts after step (b).

A lead frame with an IC chip pad with an alignment notch. A method of mounting a packaged IC chip on a lead frame at a precise angle by aligning a corner of the packaged IC chip to an alignment notch on the lead frame.

A bonded body according to an embodiment includes a substrate, a metal member, and a bonding layer. The bonding layer is provided between the substrate and the metal member. The bonding layer includes a first particle including carbon, a first region including a metal, and a second region including titanium. The second region is provided between the first particle and the first region. A concentration of titanium in the second region is greater than a concentration of titanium in the first region.

A semiconductor package includes a semiconductor chip having a first surface that is an active surface and a second surface opposing the first surface, a first redistribution portion disposed on the first surface, the first redistribution portion including a lower wiring layer electrically connected to the semiconductor chip, a thermal conductive layer disposed on the second surface of the semiconductor chip, a sealing layer surrounding a side surface of the semiconductor chip and a side surface of the thermal conductive layer, and a second redistribution portion disposed on the sealing layer, the second redistribution portion including a first upper wiring layer connected to the thermal conductive layer, the second redistribution portion including a second upper wiring layer electrically connected to the semiconductor chip.