FAN-OUT WAFER-LEVEL PACKAGE

Abstract

A fan-out wafer-level package comprising at least one integrated circuit, an internal heat spreader thermally connected to the integrated circuit either directly or via an interface layer having a thickness in sub-μm range preferably in the range of 20 nm to 500 nm, wherein the internal heat spreader is embedded in the fan-out wafer-level package.

Claims

1. A fan-out wafer-level package comprising: at least one integrated circuit, an internal heat spreader thermally connected to the integrated circuit, either directly bonded or via an interface layer having a thickness in a sub-μm range, preferably in the range of 20 nm to 500 nm, wherein the internal heat spreader is embedded in the fan-out wafer-level package.

2. The fan-out wafer-level package according to claim 1, wherein the internal head spreader has a thermal resistivity in the range of mK*mm.sup.2/W.

3. The fan-out wafer-level package according to claim 1, wherein the internal heat spreader comprises Si or a metal.

4. The fan-out wafer-level package according to claim 1 comprising at least two integrated circuits, wherein the internal heat spreader is thermally connected to the at least two integrated circuits.

5. The fan-out wafer-level package according to claim 1, wherein the internal heat spreader comprises additional heat sink structures.

6. The fan-out wafer-level package according to claim 5, wherein the additional heat sink structures are integrated cooling ribs or wherein the additional heat sink structures are micro-channels of a microfluidic cooling systems.

7. The fan-out wafer-level package according to claim 1 comprising an additional redistribution layer on a backside of the fan-out wafer-level package and at least one trough-substrate via electrically connecting the additional redistribution layer to a front of the fan-out wafer-level package, preferably to the at least one integrated circuit.

8. The fan-out wafer-level package according to claim 7 comprising at least one area with an active or passive functionality.

9. A module comprising a fan-out wafer-level package according to claim 1 and at least one additional functional element either on top or on bottom of the fan-out wafer level package.

10. The module according to claim 9 comprising a redistribution layer and at least one embedded antenna as a functional element realized within the redistribution layer or as an aperture-type antenna, which is built to be fed with a feeding structure inside the redistribution layer together with an additional antenna structure within a bonding interface area of the fan-out wafer-level package, preferably the module further comprising a lens.

11. A method for fabricating a fan-out wafer-level package comprising the steps of: providing a semiconductor wafer with at least one integrated circuit; optionally thinning down the semiconductor wafer to a desired thickness from a backside of the semiconductor wafer; optionally subsequent polishing the backside of the semiconductor wafer and/or applying an interface layer on the backside of the semiconductor wafer; singulating the semiconductor wafer into at least one die comprising the at least one integrated circuit; providing an internal heat spreader substrate comprising a heat spreader material; optionally patterning a surface of the internal heat spreader substrate or an additional permanent bonding layer deposited on the surface of the internal heat spreader substrate; depositing a dielectric layer with at least one cavity on a surface of the internal heat spreader substrate, wherein the at least one die fits into the at least one cavity of the dielectric layer; placing the at least one die in the at least one cavity; and bonding the at least one die to the internal heat spreader substrate.

12. The method according to claim 11 further comprising depositing an interface layer having a thickness in sub-μm range preferably in the range of 20 nm to 500 nm at a bottom of the at least one cavity before placing the at least one die in the at least one cavity or on the thinned semiconductor wafer.

13. The method according to claim 11, wherein depositing the dielectric layer with at least one cavity comprises: depositing a dielectric layer on the surface of the internal heat spreader substrate and subsequent patterning the dielectric layer, or placing a dielectric wafer with at least one fully prepared cavity on the surface of the internal heat spreader substrate, or placing a dielectric wafer with at least one blind cavity on the surface of the internal heat spreader substrate and thinning down the wafer to fully realize the at least one cavity.

14. The method according to claim 11, further comprising the steps of applying a redistribution layer on a top the fan-out wafer-level package, electrically connecting the at least one integrated circuit, and applying interconnections electrically connecting the redistribution layer.

15. The method according to claim 11, further comprising the step of singulating at least one individual fan-out wafer-level package.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Preferred embodiments of the invention will be discussed by way of example on the basis of the appended figures, in which:

[0060] FIG. 1 shows a cross section of a fan-out wafer-level package according to the state of the art with thermal interface material and heatsink for thermal management (FIG. 1A) and equivalent circuit of thermal resistance of a standard eWLB package (FIG. 1B);

[0061] FIG. 2 shows a cross section of an embodiment of a fan-out wafer-level package according to the invention (FIG. 2A) and an equivalent circuit of thermal resistance of this FOWLP (FIG. 2B)

[0062] FIG. 3A, 3B, 3C show an embodiment of a method for fabricating a fan-out wafer-level package according to the third aspect of the invention and the respective stages of the fan-out wafer-level package during fabrication;

[0063] FIG. 4 shows alternative method steps of a method for fabricating a fan-out wafer-level package according to the third aspect of the invention;

[0064] FIG. 5 shows a cross section of a further embodiment of a fan-out wafer-level package according to the invention;

[0065] FIG. 6 shows a cross section of a further embodiment of a fan-out wafer-level package according to the invention;

[0066] FIG. 7 shows a cross section of a further embodiment of a fan-out wafer-level package according to the invention;

[0067] FIG. 8 shows a cross section of a further embodiment of a fan-out wafer-level package according to the invention;

[0068] FIG. 9 shows a cross section of an embodiment of a module according to the second aspect of the invention;

[0069] FIG. 10 shows a cross section of a further embodiment of a module according to the second aspect of the invention;

[0070] FIG. 11 shows a cross section of a further embodiment of a fan-out wafer-level package according to the invention.

DETAILED DESCRIPTION

[0071] In the following description of the embodiments similar reference signs belong to similar elements.

[0072] FIG. 1 shows a cross section of a fan-out wafer-level package according to the state of the art with thermal interface material and heatsink for thermal management (FIG. 1A) and equivalent circuit of thermal resistance of a standard embedded wafer level ball grid array (eWLB) package (FIG. 1B) and is already discussed in the introduction. The shown FOWLP 1000a has a heat spreader 600 applied on top of the FOWLP 1000a based on a thermal interface material 500 to remove the heat from the integrated circuit 100 over the backside of the silicon chip. The equivalent circuit of the thermal resistance is also shown in FIG. 1B.

[0073] FIG. 2 shows a cross section of an embodiment of a fan-out wafer-level package 1000 according to the invention (FIG. 2A) and an equivalent circuit of thermal resistance of this FOWLP (FIG. 2B). The shown embodiment of a fan-out wafer-level package 1000 comprises one integrated circuit 100 between the fan-out. An internal heat spreader 200 is thermally connected to the integrated circuit 100 via an interface layer 210. In the shown example the interface layer 210 has a preferred thickness of 500 nm. The internal heat spreader 200 is embedded in the fan-out wafer-level package 1000. The integrated circuit 100 is arranged between fanning-out areas 110. The fanning-out is further realized with an redistribution layer RDL 300. The fan-out wafer-level package 1000 further comprises interconnections 400, herein as Cu pillars. This fan-out wafer-level package 1000 is connected using a thermal interface material 500 and an external heat sink 600 for heat management. The equivalent circuit of the thermal resistance is shown in FIG. 2B. Compared to the standard FOWLP technologies, the internal heat spreader 200 as a first heat spreader is already included within the FOWLP (R.sub.Internal heat spreader) and connected to the IC using a sub-μm/nm-range interface material (R.sub.interface) and a comparable thin IC. This combination allows to realize a low thermal resistance between the IC and the package-embedded heat spreader together with a heat spreading before the thermal interface material. The package embedded internal heat spreader ensures to provide a large area for the heat transfer over the TIM material. Based on the following equation, the R.sub.TIM can be strongly reduced because the complete package area A.sub.package is used for heat transfer compared to the small area of the IC A.sub.IC, which is used for an embedded wafer level ball grid array FOWLP.

[00001]$R_{\mathrm{TIM}}=\frac{1}{{\lambda }_{\mathrm{TIM}}}*\frac{t_{\mathrm{TIM}}}{A_{\mathrm{package}}}$

[0074] Thus an electrically conductive or non-conductive connection between IC 100 and the heat spreader 200 is realized (based on the interface layer material) with low thermal resistance, whereas for standard FOWLP especially the non-conductive interface typically creates a significant high thermal resistance because of the low thermal conductivity of insulating thermal interface materials.

[0075] FIG. 3A, 3B, 3C show an embodiment of a method for fabricating a fan-out wafer-level package according to the third aspect of the invention and the respective stages of the fan-out wafer-level package during fabrication;

[0076] A semiconductor wafer 102 (e.g. CMOS/BiCMOS or III-V on silicon) is fabricated with its front-end-of-line (FEOL) and/or backend-of-line (BEOL) in a standard fabrication approach in step S1 resulting in the semiconductor wafer 102 with a device layer 101. Dependent on the final target thickness of the actual wafer or integrated circuits, a thinning of a carrier wafer handling process might be applied. This can be realized e.g. with a temporary wafer bonding process which is typically done based on an adhesive layer 103 which is placed in between the carrier wafer 104 and the semiconductor wafer 102 with the device layer 101 (S2). The carrier wafer 104 will ensure, that the semiconductor wafer 102 can be thinned down (e.g. down to a thickness <<150 μm) in step S3 and further processed on the thinned surface. For larger target thicknesses, a carrier wafer handling might not be required and following process steps of polishing and/or deposition of permanent bonding layers can be directly applied. The semiconductor wafer 102 is thinned down to the desired thickness in step S3. A subsequent polishing based on chemical, mechanical or chemical-mechanical techniques is then applied to achieve a low surface roughness in step S4. Based on the later applied bonding technique, either the polished surface, herein preferred a silicon surface, can be directly used or an additional layer can be applied. In the following the process is shown and described for the case of an additional bonding layer. The bonding layer 105 is deposited on the backside of the thinned semiconductor wafer 102 which will act as bonding interface layer for the later permanent bonding process in S4. Different electrically/thermally conductive or non-conductive materials may be used in the bonding layer 105 (e.g. SiO2, Al2O3, Al or Cu). For heat management purposes, a material suitable for permanent bonding together with good thermal conductivity is preferable. The permanent bonding layer may serve as interface layer. In this case the bonding layer 105 has a thickness in sub-μm range preferably in the range of 20 nm to 500 nm. The whole wafer is then placed on a tape 106 and the carrier wafer 104 is debonded by a debonding techniques (e.g. thermal or mechanical debonding) in step S5. In step S6 the semiconductor wafer and its device layer are singulated into dies comprising the integrated circuit 100 e.g. by blade dicing, laser dicing or any other technique. The singulation can be also done in a so-called Dicing-before-Grinding (DBG) approach where trenches are realized from front side of the wafer and the individual dies with the integrated circuits are singulated by a backside thinning.

[0077] In step S7 in FIG. 3B an internal heat spreader substrate 200 comprising a heat spreader material is provided. A material with high thermal conductivity is preferable (e.g. Si or metal) as heat spreader material. Dependent on the permanent bonding process, either a surface of the heat spreader substrate 200 itself or a permanent bonding layer 210 can be deposited (e.g. SiO2, Al2O3, Al or Cu) and/or further patterned. In the shown embodiment a bonding layer 210 is deposited on heat spreader substrate 200. As bonding layer 105 bonding layer 210 may serve as interface layer. In some embodiments of the fan-out wafer-level package either one of the bonding layers 105 and 210 or both bonding layers together can form the interface layer.

[0078] In the following a heat spreader substrate with bonding layer 210 is used. A dielectric layer 110 is added on top of the bonding layer 210 in step S8a. This can be realized e.g. by SiO2 or any other BEOL dielectric layer, spin-coated polymer, dry-film polymer. The dielectric layer is patterned in a way that the individual dies can fit into cavities 112. As an alternative, a wafer 113, 114 (e.g. silicon, glass) with realized blind (step S8b) or full cavities (step S8c) can be also combined to create the dielectric layer with open cavities. The final cavity height should be the same like the total thickness of the integrated circuits. A specific alignment mark 111 is preferably used either in the dielectric, the bonding layer or the heat spreader substrate below to enable accurate die placement/bonding in the next step.

[0079] Dependent on the material selection and functionality, different variants and combinations of the bonding layer and the dielectric layer can be realized. For example the bonding layer can be realized only within the cavities or within the cavities and under the dielectric layer. It is also possible to use an internal heat spreader without any bonding layer using directly the internal heat spreader surface for bonding to either an interface layer on the integrated circuit or directly to the integrated circuit.

[0080] The following further fabrication is shown for the case of interface layers on both sides, thus with bonding layers 105 and 210, but can also be realized with the different aforementioned configurations. The prepared integrated circuits 100 in the respective dies are placed within the cavities preferably with ideal lateral alignment accuracy in the μm-range or below in step S9. Dependent on the applied material and permanent bonding approach, an annealing step may be applied to enable simultaneous bonding of all integrated circuits 100 which leads to a mechanical connection between the dies and the internal heat spreader 200.

[0081] A planarization step may optionally be applied to compensate local or global topography variations between the dielectric layer and the placed integrated circuits. The planarization may be achieved e.g. by an additional dielectric layer deposition with or without a subsequent chemical-mechanical polishing (CMP) or coating of a polymer layer on top. In the shown embodiment a dielectric layer 107 is deposited in step S10. For routing purposes, a multi-layer redistribution layer (RDL) is added in the shown embodiment in S11. In other embodiment the redistribution layer may be a single layer. Addition of the RDL can be achieved by different metallization techniques e.g. by standard BEOL technologies, semi-additive techniques or subtractive RDL fabrication. For a subsequent next-level of integration, interconnections e.g. based on Cu-pillars 400 or solder balls 401 are applied on top of the RDL in step S12.

[0082] Finally the substrate is singulated e.g. by blade dicing, laser dicing or any other technique to define the final package dimensions in step S13 resulting in two fan-out wafer-level packages 1000. Those packages can be directly assembled on the next substrate e.g. a printed circuit board (PCB).

[0083] In an alternative embodiment the aforementioned process can be also done using a die-to-wafer level approach for preparation of the dies. FIG. 4 shows these alternative method steps of a method for fabricating a fan-out wafer-level package according to the third aspect of the invention. Singulated individual dies comprising a device layer 101a and a semiconductor layer 102a are placed on a carrier wafer 104a with an adhesive layer 103a in step S2a. The individual dies are thinned down to the target thickness in step S3a and a polishing step may be applied to ensure a low surface roughness. Dependent on the permanent bonding process, a bonding layer 105a may be deposited in step S4a. Subsequently the thinned dies 100a can be removed/debonded from the carrier wafer by an assembly step (e.g. pick & place or die-bonding process) in step S5a To ensure a minimum mechanical stress to the thin dies, a debonding of the dies under a small tilt is preferable compared to a parallel debonding process.

[0084] FIG. 5 shows a cross section of a further embodiment of a fan-out wafer-level package 2000 according to the invention. In this embodiment in the internal heat spreader 200 a heatsink is directly implemented by structuring the internal heat spreader 200 itself with cooling ribs 250. With this embodiment the thermal management can be realized easily without any additional TIM and/or external heat spreader because the fan-out wafer level package already includes the overall thermal management components. Although the combined heat spreader/heatsink based on the internal heat spreader might be less performant compared to standalone components, the reduced thermal path with a minimum number of thermal interfaces due to the eliminated TIM and external heat spreader/heatsink can provide very low thermal resistance with a significant lower volume.

[0085] FIG. 6 shows a cross section of a further embodiment of a fan-out wafer-level package 3000 according to the invention. Herein a similar concept to one in FIG. 5 is applied to directly embed a microfluidic cooling inside the proposed FOWLP. The internal heat spreader 200 in this embodiment includes micro-channels 220, which can be connected using a flexible microfluidic interface 240 with in- and outlets 230.

[0086] FIG. 7 shows a cross section of a further embodiment of a fan-out wafer-level package 5000 according to the invention. In the shown embodiment an additional redistribution layer 320 is place on the backside of the fan-out wafer-level package 5000, which is built-up similar to the one shown in FIG. 2 but with additional through-substrate vias (TSV) 260 to realize a connection from front to backside. The backside redistribution layer 320 can be used e.g. for the implementation of high-Q passives using thick metals or even allows for the assembly of surface-mounted devices (SMD)-like components.

[0087] FIG. 8 shows a cross section of a further embodiment of a fan-out wafer-level package 6000 according to the invention. Fan-out wafer-level package 6000 is similar to fan-out wafer-level package 5000 of FIG. 7. Herein the internal heat spreader 200 comprises additional active or passive functionalities 270. Thus the internal heat spreader can be considered as functionalized heat sink with active/passive functionality.

[0088] FIG. 9 shows a cross section of an embodiment of a module 4001 according to the second aspect of the invention. The module 4001 comprises a fan-out wafer-level package 4000, which is built-up similar to the fan-out-wafer-level package 1000 of FIG. 2 and an embedded antenna 310 within the redistribution layer 300 on bottom of the fan-out wafer level package 4000. As alternative an aperture-type antenna may be used, which can be feed with a structure inside the redistribution layer together with an additional antenna structure within the bonding interface area. In the shown embodiment additional lenses 701, 702, 703 are placed directly on top of the package backside. Herein three types of lenses are shown, of which each may be used alone or in combination. Lens 701 is a hemispherical lens. Lenses 702 and 703 or meta-material based lenses, wherein lens 703 is a pillar-type meta-material lens and lens 702 is a hole-type meta-material lens. Beside the functionality for the antenna and radiation the lens can directly act also as heatsink thus no additional heatsink is required. In this case meta-material based antennas with etched pillars are advantageous because the area for heat transfer based on natural/forced convection is strongly increased compared to hemispherical lenses.

[0089] FIG. 10 shows a cross section of a further embodiment of a module 7001 according to the second aspect of the invention. Fan-out wafer-level package 7000 is similar built to fan-out wafer-level package 5000 of FIG. 7. Based on the additional backside redistribution layer an additional functional element 800 is assembled on top of the fan-out wafer-level package 7000. Thus this fan-out wafer-level package is directly used for 3D integration, here for 3D stacking.

[0090] FIG. 11 shows a cross section of a further embodiment of a fan-out wafer-level package 8000 according to the invention. Fan-out wafer-level package 8000 is similar built to fan-out wafer-level package 1000 of FIG. 2. In contrast to fan-out wafer-level package 1000 in fan-out wafer-level package 8000 the internal heat spreader 200 and the interface layer 210 are arranged between the fan-out areas 110.

REFERENCE SIGNS

[0091] 100 integrated circuit [0092] 1000 fan-out wafer-level package [0093] 1000a fan-out wafer-level package [0094] 101 device layer [0095] 102 semiconductor wafer [0096] 103 adhesive layer [0097] 104 carrier wafer [0098] 105 bonding layer [0099] 106 tape [0100] 107 dielectric layer [0101] 110 fanning-out area [0102] 111 alignment mark [0103] 112 cavity [0104] 113 wafer [0105] 114 wafer [0106] 200 internal heat spreader [0107] 210 interface layer [0108] 300 redistribution layer [0109] 400 interconnections [0110] 500 thermal interface material [0111] 600 heat spreader [0112] 100a thinned die [0113] 101a device layer [0114] 102a semiconductor layer [0115] 103a adhesive layer [0116] 104a carrier wafer [0117] 105a bonding layer [0118] 220 micro-channels [0119] 230 outlets [0120] 240 microfluidic interface [0121] 250 cooling ribs [0122] 260 through-substrate via [0123] 270 passive functionality [0124] 310 embedded antenna [0125] 320 additional redistribution layer [0126] 401 balls [0127] 701 lens [0128] 702 lens [0129] 703 lens [0130] 800 additional functional element [0131] 2000 fan-out wafer-level package [0132] 3000 fan-out wafer-level package [0133] 4000 fan-out wafer-level package [0134] 4001 module [0135] 5000 fan-out wafer-level package [0136] 6000 fan-out wafer-level package [0137] 7000 fan-out wafer-level package [0138] 7001 module [0139] 8000 fan-out wafer-level package