A pillar structure is provided. The pillar structure includes a plurality of pillars. Each of the pillars include a capping material layer formed in a pit etched into a template wafer, a conductive plug formed on the capping material layer, a base layer formed on the conductive plug, and an attach material layer formed on the base layer. The pillars are joined vertically together to form the pillar structure.

A chip on film package is provided. The chip on film package includes a film substrate with a base film, a conductive pad extending in a first direction on the base film, and a conductive line pattern extending from the conductive pad; a semiconductor chip provided on the film substrate; and a bump structure provided between the semiconductor chip and the conductive pad. A first peripheral wall and a second peripheral wall of the bump structure extend in the first direction and define a trench, a portion of the conductive pad is provided in the trench, and the conductive pad is spaced apart from at least one of the first peripheral wall and the second peripheral wall.

A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, and a first chip connection structure disposed between the first semiconductor chip and the second semiconductor chip. The first chip connection structure includes a first insertion connection structure connected to the first semiconductor chip, a first recess connection structure connected to the second semiconductor chip, and a first contact layer interposed between the first insertion connection structure and the first recess connection structure. The first recess connection structure includes a base and a side wall which defines a recess. A portion of the first insertion connection structure is disposed in the recess. A portion of the first contact layer is disposed in the recess, and the first contact layer covers at least a portion of a bottom surface of the side wall.

Provided is a method of manufacturing a semiconductor device including a bump interconnect structure. In the method of manufacturing the semiconductor device, a first substrate including a connection pad is formed, and a bump including a solder layer and a metal post protruding from the solder layer are formed on the connection pad. A second substrate including a bump land may be formed. The first substrate may be disposed on the second substrate so that a protruding end of the metal post contacts the bump land, and the solder layer may be reflowed. Accordingly, it possible to interconnect the metal post to the bump land.

A light emitting diode includes: a light emitting layer arranged on at least part of a first semiconductor layer, and a second semiconductor layer; a local defect region over a portion of the second semiconductor layer and extending downward to the first semiconductor layer; a metal layer over a portion of the second semiconductor layer; an insulating layer covering the metal layer, the second and first semiconductor layers in the local defect region, with opening structures over the local defect region and the metal layer, respectively; and an electrode structure over the insulating layer and having a first layer and a second layer, and including a first-type electrode region and a second-type electrode region; wherein an upper surface and a lower surface of the first layer are not flat, and a lower surface of the second layer are both flat.

Methods, systems, apparatus, and articles of manufacture to produce nano-roughened integrated circuit packages are disclosed. An example integrated circuit (IC) package includes a substrate, a semiconductor die, and a metal interconnect to electrically couple the semiconductor die to the substrate, the metal interconnect including a nano-roughened surface.

A method for manufacturing a semiconductor device includes providing a semiconductor element having an electrode terminal, forming a resist on the semiconductor element, the resist having a first surface facing the electrode terminal and a second surface opposite to the first surface, providing an imprint mold having a third surface and a protrusion protruding from the third surface, forming an opening in the resist by disposing the imprint mold on the second surface of the resist and inserting the protrusion into the resist, the third surface of the imprint mold facing the second surface of the resist, the protrusion being aligned with the electrode terminal, curing the resist by applying energy to the resist, widening the opening in a radial direction of the opening by causing the resist to react with a developer, and forming a bump by filling the opening with metal, in which the forming of the opening in the resist is performed in a state where a gap is provided between the second surface of the resist and the third surface of the imprint mold.

The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.

A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects comprises a first pillar interconnect. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width and a second pillar interconnect portion comprising a second width that is different than the first width.

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.