Patent classifications
H01L2224/13616
POLYMER LID WAFER-LEVEL PACKAGE WITH AN ELECTRICALLY AND THERMALLY CONDUCTIVE PILLAR
An apparatus include a device substrate having an upper surface, and a frame layer having an upper surface. The frame layer is disposed over the upper surface of the device substrate, and a first opening exists in the frame layer. The apparatus also includes a seed layer disposed over the device substrate and substantially bounded by the first opening; and a lid layer having an upper surface. The lid layer is disposed over the upper surface of the frame layer. A second opening exists in the lid layer, and the second opening is aligned with the first opening. The apparatus also includes an electrically and thermally conductive pillar disposed in the first opening and the second opening.
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.
SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A method for fabricating a semiconductor structure is provided. The method includes: providing a semiconductor chip comprising an active surface; forming a conductive bump over the active surface of the semiconductor chip; and coupling the conductive bump to a substrate. The conductive bump includes a plurality of bump segments including a first group of bump segments and a second group of bump segments. Each bump segment has a same segment thickness in a direction orthogonal to the active surface of the semiconductor chip, and each bump segment has a volume defined by a multiplication of the same segment thickness with an average cross-sectional area of the bump segment in a plane parallel to the active surface of the semiconductor chip. A ratio of a total volume of the first group of bump segments to a total volume of the second group of bump segments is between 0.03 and 0.8.
Polymer layer on metal core for plurality of bumps connected to conductive pads
A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.
Polymer layer on metal core for plurality of bumps connected to conductive pads
A semiconductor chip, a display device or an electronic device includes a substrate, one or more conductive pads disposed on the substrate, and one or more bumps electrically connected to the one or more conductive pads, in which the one or more bumps includes a metal core, a polymer layer disposed over a surface of the metal core, and a conductive coating layer disposed over a surface of the polymer layer and electrically connected to the one or more conductive pads.
Semiconductor Die Singulation and Structures Formed Thereby
An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.
Semiconductor device and method for manufacturing the same
According to one embodiment, a semiconductor device includes a first semiconductor substrate having a first wiring electrode on a first surface thereof, a first protective layer on the semiconductor substrate, having an opening therethrough at the location of first wiring electrode, a first bump electrode in the opening of the first protective layer, the first bump electrode including a base overlying the wiring electrode and an opposed bump receiving surface, and a first bump comprising a bump diameter of 30 m or less connected to the first bump electrode. The width of the base of the first bump electrode within the opening is equal to or less than 1.5 times the thickness of the first protective layer.
Multiple bond via arrays of different wire heights on a same substrate
Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (first wires) extend from a surface of the substrate. Second wire bond wires (second wires) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.
Multiple bond via arrays of different wire heights on a same substrate
Apparatuses relating generally to a substrate are disclosed. In such an apparatus, first wire bond wires (first wires) extend from a surface of the substrate. Second wire bond wires (second wires) extend from the surface of the substrate. The first wires and the second wires are external to the substrate. The first wires are disposed at least partially within the second wires. The first wires are of a first height. The second wires are of a second height greater than the first height for coupling of at least one electronic component to the first wires at least partially disposed within the second wires.
VISIBILITY EVENT NAVIGATION METHOD AND SYSTEM
A method of visibility event navigation includes receiving, via processing circuitry of a client device, a first visibility event packet from a server, the first visibility event packet including information representing 3D surface elements of an environmental model that are occluded from a first viewcell and not occluded from a second viewcell, the first and second viewcells representing spatial regions of a specified navigational route within a real environment modeled by the environmental model. The method also includes acquiring, surface information representing the visible surfaces of the real environment at a sensor and determining, a position in the real environment by matching the surface information to the visibility event packet information. The method further includes transmitting, the position from the client device to the server and receiving a second visibility event packet from the server if the at least one position is within the specified navigational route.