A driving chip and a display device, relating to the technical field of driving chip for displays, are disclosed. A surface of the driving chip has a first edge and a second edge opposite to each other. The driving chip includes connecting bumps and supporting bumps, which are arranged along the first edge to form at least one first bump column, and at either end of the first bump column, there is at least one of the supporting bumps; the connecting bumps and the supporting bumps are arranged along the second edge to form at least one second bump column, and at either end of the second bump column, there is at least one of the supporting bumps. A surface of the driving chip according to embodiments of the invention has bump columns, a supporting bump is disposed at an end of a bump column, and acts to support the driving chip favorably. Thus, upon bonding and packaging, the driving chip can bear a force in equilibrium as a whole, and occurrence of a problem of impression defectiveness is avoided.

A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and a method of manufacturing thereof, that comprises a first semiconductor die, a plurality of adhesive regions spaced apart from each other on the first semiconductor die, and a second semiconductor die adhered to the plurality of adhesive regions.

A module assembly device (402) is configured for assembling a module assembly (114) for a detector array (110) of an imaging system (100). The module assembly device includes a base (400) having a long axis (401). The module assembly device further includes a first surface (406) of the base and side walls (408) protruding perpendicular up from the first surface and extending in a direction of the long axis along at least two sides of the base. The first surface and side walls form a recess (404) configured to receive the module substrate on the surface and within the side walls. The module assembly device further includes protrusions (403) protruding from the side walls in a direction of the side walls. The protrusions and side walls interface forming a ledge which serves as a photo-detector array tile support (410) configured to receive the photo-detector array tile (118) over the ASIC and the module substrate.

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

A semiconductor package structure includes a semiconductor die surface having a narrower pitch region and a wider pitch region adjacent to the narrower pitch region, a plurality of first type conductive pillars in the narrower pitch region, each of the first type conductive pillars having a copper-copper interface, and a plurality of second type conductive pillars in the wider pitch region, each of the second type conductive pillars having a copper-solder interface. A method for manufacturing the semiconductor package structure described herein is also disclosed.

To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a semiconductor substrate having an insulating film in which an opening that exposes each of a plurality of electrode pads is formed is provided, and a flux member including conductive particles is arranged over each of the electrode pads. Thereafter, a solder ball is arranged over each of the electrode pads via the flux member, and is then heated via the flux member so that the solder ball is bonded to each of the electrode pads. The width of the opening of the insulating film is smaller than the width (diameter) of the solder ball.

A method comprises depositing a protection layer over a first substrate, wherein the first substrate is part of a first semiconductor die, forming an under bump metallization structure over the protection layer, forming a connector over the under bump metallization structure, forming a first dummy plane along a first edge of a top surface of the first semiconductor die and forming a second dummy plane along a second edge of the top surface of the first semiconductor die, wherein the first dummy plane and the second dummy plane form an L-shaped region.

A package structure is provided comprising a die, a redistribution layer, at least one integrated passive device (IPD), a plurality of solder balls and a molding compound. The die comprises a substrate and a plurality of conductive pads. The redistribution layer is disposed on the die, wherein the redistribution layer comprises first connection structures and second connection structures. The IPD is disposed on the redistribution layer, wherein the IPD is connected to the first connection structures of the redistribution layer. The plurality of solder balls is disposed on the redistribution layer, wherein the solder balls are disposed and connected to the second connection structures of the redistribution layer. The molding compound is disposed on the redistribution layer, and partially encapsulating the IPD and the plurality of solder balls, wherein top portions of the solder balls and a top surface of the IPD are exposed from the molding compound.

A multi-chip package structure includes a first chip, a second chip, a circuit layer, a plurality of first conductive bumps, a plurality of second conductive bumps and an underfill. The first chip has a chip bonding region, a plurality of first inner pads and first outer pads. The circuit layer is disposed on the first chip and includes a plurality of insulating layers and at least one metal layer. The insulating layers have a groove disposed between the first inner pads and the first outer pads and surrounding the first inner pads. The first conductive bumps are disposed on the first outer pads. The second chip is flipped on the chip bonding region. Each first inner pad is electrically connected to a second pad of the second chip through the second conductive bump. The underfill is disposed between the first and second chips and covers the second conductive bumps.

Provided is a disclosure for optimizing the number of semiconductor devices on a wafer/substrate. The optimization comprises laying out, cutting, and packaging the devices efficiently.