Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/10
Bump connectors; Manufacturing methods related thereto
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H01L2224/15
Structure, shape, material or disposition of the bump connectors after the connecting process
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H01L2224/16
of an individual bump connector
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H01L2224/16151
the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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H01L2224/16153
the body and the item being arranged next to each other, e.g. on a common substrate
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H01L2224/16195
the item being a discrete passive component
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H01L2224/16197
the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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H01L2224/16197

INTEGRATED CIRCUIT STRUCTURES WITH INTERPOSERS HAVING RECESSES
20170170109 · 2017-06-15 ·

Disclosed herein are integrated circuit (IC) structures having interposers with recesses. For example, an IC structure may include: an interposer having a resist surface; a recess disposed in the resist surface, wherein a bottom of the recess is surface-finished; and a plurality of conductive contacts located at the resist surface. Other embodiments may be disclosed and/or claimed.