A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated.

A radar device includes: a substrate including multiple high-frequency conductor layers arranged on a front surface; a semiconductor component in contact with the high-frequency conductor layers via conductive members; and an adhesive that bonds the semiconductor component to the front surface of the substrate. The semiconductor component has a bottom surface and a first side surface facing in a first direction. All the multiple high-frequency conductor layers include at least high-frequency conductor layers bending in a plane of the front surface and thereby extend, on the front surface, from inside ends facing the bottom surface to outside ends positioned in the first direction from the first side surface. The adhesive is in contact with the front surface except for the sites of the multiple high-frequency conductor layers formed and in contact with the side surfaces of the semiconductor component.

A package comprising a substrate comprising a plurality of interconnects, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, and an interconnect device coupled to the substrate. The first integrated device, the second integrated device, the interconnect device and the substrate are configured to provide an electrical path for an electrical signal between the first integrated device and the second integrated device, that extends through at least the substrate, through the interconnect device and back through the substrate. The electrical path includes at least one interconnect that extends diagonally.

An electronic substrate includes: a body having a mounting surface; an electronic component having an opposed surface facing the mounting surface; and an adhesive layer that bonds the electronic component to the mounting surface. The mounting surface has a storage recess that stores at least a part of the adhesive layer. The storage recess is located from a first area overlapping the opposed surface to a second area not overlapping the opposed surface in plan view.

An electronic substrate includes: a body having a mounting surface; an electronic component having an opposed surface facing the mounting surface; and an adhesive layer that bonds the electronic component to the mounting surface. The mounting surface has a storage recess that stores at least a part of the adhesive layer. The storage recess is located from a first area overlapping the opposed surface to a second area not overlapping the opposed surface in plan view.

A substrate that includes a core layer comprising a first surface and a second surface, at least one first dielectric layer located over a first surface of the core layer, at least one second dielectric layer located over a second surface of the core layer, high-density interconnects located over a surface of the at least one second dielectric layer, interconnects located over the surface of the at least one second dielectric layer, and a solder resist layer located over the surface of the at least one second dielectric layer. A first portion of the solder resist layer that is touching the high-density interconnects includes a first thickness that is equal or less than a thickness of the high-density interconnects. A second portion of the solder resist layer that is touching the interconnects includes a second thickness that is greater than a thickness of the interconnects.

A high-frequency module (1) includes a substrate (10), a first electronic component (30) and a second electronic component (40) mounted on a main surface (10a) of the substrate (10). The substrate (10) has a protruding portion (20) projecting from the main surface (10a), the first electronic component (30) is mounted in a region of the main surface (10a) different from a region in which the protruding portion (20) is provided, and the second electronic component (40) is mounted on the protruding portion (20).

A laser reflow apparatus reflows solder bumps disposed on a side of a semiconductor chip in a workpiece and included in an irradiation range on the workpiece by applying a laser beam to an opposite side of the semiconductor chip. The laser reflow apparatus includes a spatial beam modulation unit including a laser power density setting function to locally set the laser power density in the irradiation range of a laser beam emitted from a laser beam source, and an image focusing unit including an image focusing function to focus the laser beam emitted from the laser beam source and apply the focused laser beam to the irradiation range on the workpiece.

A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the 3DIC. The cooling element includes a plurality of individually controllable cooling modules disposed at a first plurality of locations relative to the 3DIC. Each of the cooling modules includes a cold pole and a heat sink. The cold pole is configured to absorb heat from the 3DIC. The heat sink is configured to dissipate the heat absorbed by the cold pole and is coupled to the cold pole via an N-type semiconductor element and via a P-type semiconductor element. A temperature sensing element includes a plurality of thermal monitoring elements disposed at a second plurality of locations relative to the 3DIC for measuring temperatures at the second plurality of locations. The measured temperatures control the plurality of cooling modules.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.