A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

A chip packaging method and package structure, the package structure including a substrate, a sensing chip coupled to the substrate, a plastic package layer located on the substrate, and a covering layer located on the plastic package layer and a first surface of the sensing chip; the sensing chip including the first surface and a second surface opposite to the first surface, and further including a sensing area located on the first surface; the second surface of the sensing chip faces towards the substrate; and the plastic package layer encloses the sensing chip, and the surface of the plastic package layer is flush with the first surface of the sensing chip.

A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact.

A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.

Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via

A semiconductor chip includes an electrical contact layer covered by a passivation layer. The semiconductor chip is encapsulated in an encapsulation formed by laser-direct-structuring (LDS) material. Laser beam energy is applied to the encapsulation to structure therein a through via passing through the encapsulation and removing the passivation layer at a bonding site of the electrical contact layer of the at least one semiconductor chip. The through via structured in the encapsulation is made electrically conductive so that the electrically-conductive through via is electrically coupled to, optionally in direct contact with, the electrical contact layer at a bonding site where the passivation layer has been removed.

The semiconductor device includes first and second semiconductor elements. Each element has an obverse surface and a reverse surface, with a first electrode arranged on the reverse surface, and with a second electrode arranged on the obverse surface. The semiconductor device further includes: a first lead having an obverse surface and a reverse surface; an insulating layer covering the first lead, the first semiconductor element and the second semiconductor element; a first electrode connected to the second electrode of the first semiconductor element; and a second electrode connected to the first lead. The first semiconductor element and the first lead are bonded to each other with the reverse surface of the first semiconductor element facing the lead obverse surface. The second semiconductor element and the first lead are bonded to each other with the reverse surface of the second semiconductor element facing the lead reverse surface.

A semiconductor device includes a support substrate with leads arranged therearound, a semiconductor die on the support substrate, and a layer of laser-activatable material molded onto the die and the leads. The leads include proximal portions facing towards the support substrate and distal portions facing away from the support substrate. The semiconductor die includes bonding pads at a front surface thereof which is opposed to the support substrate, and is arranged onto the proximal portions of the leads. The semiconductor device has electrically-conductive formations laser-structured at selected locations of the laser-activatable material. The electrically-conductive formations include first vias extending between the bonding pads and a front surface of the laser-activatable material, second vias extending between the distal portions of the leads and the front surface of the laser-activatable material, and lines extending at the front surface of the laser-activatable material and connecting selected first vias to selected second vias.

Provided is a wiring substrate and its manufacturing method in which a thick wiring layer capable of being applied with a large current and a thin wiring layer capable of being subjected to microfabrication coexist in the same layer. The wiring substrate includes: an insulating film located over a first wiring and having a via; and a second wiring over the insulating film. The second wiring has a stacked structure including a first layer and a second layer covering the first layer. The second layer is in direct contact with the first wiring in the via. A thickness of the second layer in a region overlapping with the first layer is different from a thickness of the second layer in the via.

A semiconductor laser component including a semiconductor chip arranged to emit laser radiation, a cladding that is electrically insulating and covers the semiconductor chip in places, and a bonding layer that electrically conductively connects the semiconductor chip to a first connection point, wherein the semiconductor chip includes a cover surface, a bottom surface, a first front surface, a second front surface, a first side surface and a second side surface, the first front surface is arranged to decouple the laser beam, the cladding covers the semiconductor chip at least in places on the cover surface, the second front surface, the first side surface and the second side surface, and the bonding layer on the cladding extends from the cover surface to the first connection point.