A semiconductor device includes a semiconductor element including first, second and third electrodes, where energization of the first and third electrodes is controlled by voltage application to the second electrode. The semiconductor device further includes a first lead connected to the first electrode, a second lead connected to the second electrode, a third lead connected to the third electrode, a fourth lead, and a sealing resin covering at least the semiconductor element. The third lead is exposed from the sealing resin to a second side in a thickness direction. The fourth lead is bonded to the semiconductor element and exposed from the sealing resin to the second side in the thickness direction. The semiconductor element includes a switching function unit. The impedance of a path from the switching function unit to the fourth lead is larger than that of a path from the switching function unit to the third lead.

A lead frame has a metal base, a silver-plated layer, and a silver oxide layer. The silver-plated layer is formed between the metal base and the silver oxide layer. The silver oxide layer has a polar outer surface and a thickness of equal to or more than 1.3 nanometers. The silver oxide layer is beneficial to increase the adhesive strength between the lead frame and the molding compound and avoid delamination of the molding compound from the lead frame, so the lead frame of the present invention can pass a more severe moisture sensitivity level when exposed to the environment.

An electronic component includes an integrated circuit chip and a package surrounding the integrated circuit chip. The electronic component includes at least a first conductive region at least partially coating one side of the integrated circuit chip. The first conductive region includes an alloy predominantly comprising bismuth.

The present disclosure pertains to a die bonding structure. The die bonding structure includes a carrier substrate, a sintered layer, a nano-twinned layer, an adhesive layer and a chip. The sintered layer is located on the carrier substrate. The nano-twinned layer is located on the sintered layer, in which the surface of the nano-twinned layer has [111] crystal orientation with a density greater than 80%, in which the nano-twinned layer comprises parallel-arranged twin boundaries, the parallel-arranged twin boundaries comprise more than 40% [111] crystal orientation, and the spacing between the parallel-arranged twin boundaries is 10 to 100 nm. The adhesive layer is located on the nano-twinned layer. The chip is located on the adhesive layer.

A driving backplane, a transfer method for a light-emitting diode chip (21), and a display apparatus. The driving backplane comprises: a base substrate (10), a driving circuit, a plurality of electromagnetic structures (13), and a plurality of contact electrodes (12). The plurality of electromagnetic structures (13) in the driving backplane are symmetrically arranged relative to a first straight line (L1) and a second straight line (L2). A current signal can be applied to each electromagnetic structure (13) by means of the driving circuit. Stress generated by a transfer carrier plate (20) according to the magnetic force of each electromagnetic structure (13) moves the transfer carrier plate (20). When the transfer carrier plate (20) is stress balanced in each direction parallel to the surface of the transfer carrier plate (20), the light-emitting diode chip (21) is precisely aligned to corresponding contact electrodes (12).

A joining structure including a joining part that joins two objects, in which the joining part includes a first metal phase containing Bi as a main component, the first metal phase having a granular shape with an average size of 0.5 m to 5 m, and a second metal phase containing Cu as a main component and containing Sn and In, the first metal phase is dispersed in the second metal phase, and the joining part has a metal composition ratio of Sn: 9.4 mass % to 19.4 mass %, Bi: 26.7 mass % to 36.7 mass %, In: 6.5 mass % to 16.5 mass %, and Cu: a balance.

A device package includes a diamond heat spreader and a filler material bonded to a first side of the diamond heat spreader. A first integrated circuit (IC) device coupled to a second side of the diamond heat spreader opposite the filler material. A second IC device wherein a first side of the filler material opposite of a side bonded to the heat spreader shares a horizontal plane with a top side of the second IC device.

A package structure includes a substrate, a chip disposed on the substrate and having a backside surface away from the substrate, a heat sink disposed above the substrate and having a surface facing the back side surface, and a thermal interface material disposed between the chip and the heat sink. There is no organic adhesive between the chip and the heat sink. A method for forming the package structure is also provided.