Patent classifications
H01L2224/29644
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.
PRE-PLATED SUBSTRATE FOR DIE ATTACHMENT
A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.
PRE-PLATED SUBSTRATE FOR DIE ATTACHMENT
A method for attaching a semiconductor die to a substrate includes providing a substrate that includes an attachment layer at a surface of the substrate. The attachment layer is covered by a protective flash plating layer. The protective flash plating layer has a reflow temperature less than or equal to a reflow temperature of the attachment layer. The method further includes preheating the substrate to a temperature greater than or equal to a reflow temperature of the attachment layer, attaching a semiconductor die to the attachment layer, and cooling the substrate and semiconductor die.
UV-curable anisotropic conductive adhesive
Illustrative embodiments of anisotropic conductive adhesive (ACA) and associated methods are disclosed. In one illustrative embodiment, the ACA may comprise a binder curable using UV light and a plurality of particles suspended in the binder. Each of the plurality of particles may comprise a ferromagnetic material coated with a layer of electrically conductive material. The electrically conducting material may form electrically conductive and isolated parallel paths when the ACA is cured using UV light after being subjected to a magnetic field.
UV-curable anisotropic conductive adhesive
Illustrative embodiments of anisotropic conductive adhesive (ACA) and associated methods are disclosed. In one illustrative embodiment, the ACA may comprise a binder curable using UV light and a plurality of particles suspended in the binder. Each of the plurality of particles may comprise a ferromagnetic material coated with a layer of electrically conductive material. The electrically conducting material may form electrically conductive and isolated parallel paths when the ACA is cured using UV light after being subjected to a magnetic field.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
The present invention provides a method for producing a semiconductor device, including: a semiconductor chip-mounting step of subsequently pressing a plurality of semiconductor chips by a first pressing member to respectively bond the plurality of semiconductor chips to a plurality of mounting areas provided on a substrate, wherein the bonding is performed in a state where adhesive sheets are respectively interposed between the plurality of semiconductor chips and the plurality of mounting areas, each of the adhesive sheets includes sinterable metal particles that can be sintered by heating at a temperature of 400° C. or less, and the first pressing member is heated to a temperature, at which the sinterable metal particles can be sintered.
SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
The present invention provides a method for producing a semiconductor device, including: a semiconductor chip-mounting step of subsequently pressing a plurality of semiconductor chips by a first pressing member to respectively bond the plurality of semiconductor chips to a plurality of mounting areas provided on a substrate, wherein the bonding is performed in a state where adhesive sheets are respectively interposed between the plurality of semiconductor chips and the plurality of mounting areas, each of the adhesive sheets includes sinterable metal particles that can be sintered by heating at a temperature of 400° C. or less, and the first pressing member is heated to a temperature, at which the sinterable metal particles can be sintered.
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.
Semiconductor device and method for manufacturing the same
A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.
SEMICONDUCTOR CHIP SUITABLE FOR 2.5D AND 3D PACKAGING INTEGRATION AND METHODS OF FORMING THE SAME
The present disclosure relates to a semiconductor chip that includes a substrate, a metal layer, and a number of component portions. Herein, the substrate has a substrate base and a number of protrusions protruding from a bottom surface of the substrate base. The substrate base and the protrusions are formed of a same material. Each of the protrusions has a same height. At least one via hole extends vertically through one protrusion and the substrate base. The metal layer selectively covers exposed surfaces at a backside of the substrate and fully covers inner surfaces of the at least one via hole. The component portions reside over a top surface of the substrate base, such that a certain one of the component portions is electrically coupled to a portion of the metal layer at the top of the at least one via hole.