A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

An electronic device includes a substrate and a wiring. The wiring is provided above the substrate and includes a NiB layer and a copper layer provided on the NiB layer. The NiB layer contains 3.2% by weight to 5% by weight of boron.

Methods for bonding substrates used, for example, in substrate-level packaging, are provided herein. In some embodiments, a method for bonding substrates includes: performing electrochemical deposition (ECD) to deposit at least one material on each of a first substrate and a second substrate, performing chemical mechanical polishing (CMP) on the first substrate and the second substrate to form a bonding interface on each of the first substrate and the second substrate, positioning the first substrate on the second substrate so that the bonding interface on the first substrate aligns with the bonding interface on the second substrate, and bonding the first substrate to the second substrate using the bonding interface on the first substrate and the bonding interface on the second substrate.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A method of manufacturing a semiconductor device of the present disclosure includes the steps of sequentially forming an adhesion-improving film, a Pt film, a Sn film, and an Au film on a semiconductor wafer through vapor deposition; dicing the semiconductor wafer to obtain a semiconductor element; sequentially forming a Ni film and an Au film on a substrate through vapor deposition; and laminating the semiconductor element and the substrate so that the Au film formed on the semiconductor element and the Au film formed on the substrate face each other, followed by joining the semiconductor element and the substrate through heating.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A method of manufacturing a semiconductor device of the present disclosure includes the steps of sequentially forming an adhesion-improving film, a Pt film, a Sn film, and an Au film on a semiconductor wafer through vapor deposition; dicing the semiconductor wafer to obtain a semiconductor element; sequentially forming a Ni film and an Au film on a substrate through vapor deposition; and laminating the semiconductor element and the substrate so that the Au film formed on the semiconductor element and the Au film formed on the substrate face each other, followed by joining the semiconductor element and the substrate through heating.

An inductor conductor design which minimizes the impact of skin effect in the conductors at high frequencies in integrated circuits and the method of manufacture thereof is described herein.

Semiconductor packages are provided. In one example, a semiconductor package may include a substrate comprising a through hole extending through the substrate. The semiconductor package may include a semiconductor die on the substrate. The semiconductor die may be overlapping the through hole. The through hole in the substrate may be at least partially filled with an electroless deposited portion.