Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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H01L2224/01
Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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H01L2224/34
Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
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H01L2224/36
Structure, shape, material or disposition of the strap connectors prior to the connecting process
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H01L2224/37
of an individual strap connector
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H01L2224/37001
Core members of the connector
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H01L2224/371
with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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H01L2224/37117
the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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H01L2224/3712
Antimony [Sb] as principal constituent
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H01L2224/3712

SEMICONDUCTOR DEVICE HAVING A WIRING MEMBER WITH AN UNEVEN BONDING SURFACE
20250343198 · 2025-11-06 · ·

A semiconductor device, including: a semiconductor chip having a first electrode and a second electrode respectively on a upper surface and a lower surface thereof; and a wiring member including a bonding portion having a bonding surface, which is bonded to the first electrode with a solder therebetween, and a rising portion extending from an outer periphery of the bonding portion, the bonding surface being located, in a plan view of the semiconductor device, within the upper surface of the semiconductor chip. The bonding surface has an outer edge area and a middle area. In a height direction of the semiconductor device, a first height from the outer edge area of the bonding surface to the upper surface of the semiconductor chip is greater than a second height from the middle area of the bonding surface to the upper surface of the semiconductor chip.