A method of manufacturing packages is disclosed. In one example, the method comprises providing an electrically conductive sheet being continuous at least in a mounting region, mounting first main surfaces of a plurality of electronic components on the continuous mounting region of the sheet and forming interconnect structures for electrically coupling second main surfaces of the electronic components with the sheet. The second main surfaces oppose the first main surfaces. After the forming, structuring the sheet.

To suppress a temperature rise of a chip accompanying a production of large output by a power converter, and to reduce a size of the power converter. A power semiconductor device includes: a first power semiconductor element to configure an upper arm of an inverter circuit; a second power semiconductor element to configure a lower arm of the inverter circuit; a first lead frame to transmit power to the first power semiconductor element; a second lead frame to transmit power to the second power semiconductor element; a first gate lead frame to transmit a control signal to the first power semiconductor element; and a sealing member to seal the first power semiconductor element, the second power semiconductor element, the first lead frame, the second lead frame, and the first gate lead frame. In the power semiconductor device, a through-hole is formed in the sealing member, and a part of the first gate lead frame and a part of the second lead frame are exposed to an inner peripheral surface of the through-hole.

A semiconductor device includes a first lead portion and a second lead portion spaced from each other in a first direction. A semiconductor chip is mounted to the first lead portion. A first connector has a first portion contacting a second electrode on the chip and a second portion connected to the second lead portion. A second connector has third portion that contacts the second electrode, but at a position further away than the first portion, and a fourth portion connected to the second portion. At least a part of the second connector overlaps a part of the first connector between the first lead portion and the second lead portion.

A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.

To provide a film which is excellent in releasing property with respect to a resin sealed portion and excellent in low migration property and peeling property with respect to a semiconductor chip, a source electrode or a sealing glass and which is suitable as a mold release film for producing a semiconductor element having a part of the surface of a semiconductor chip, source electrode or sealing glass exposed. A film 1 which comprises a substrate 3 and an adhesive layer 5, wherein the storage elastic modulus at 180° C. of the substrate 3 is from 10 to 100 MPa, and the adhesive layer 5 is a reaction cured product of a composition for adhesive layer comprising a specific acrylic polymer and a polyfunctional isocyanate compound, wherein the number of moles M.sub.OH of hydroxy groups and the number of moles M.sub.COOH of carboxy groups, derived from the acrylic polymer, and the number of moles M.sub.NCO of isocyanate groups derived from the polyfunctional isocyanate compound, satisfy a specific relation, and which is suitable as a mold release film for producing a semiconductor element.

A semiconductor device includes a first lead portion and a second lead portion spaced from each other in a first direction. A semiconductor chip is mounted to the first lead portion. A first connector has a first portion contacting a second electrode on the chip and a second portion connected to the second lead portion. A second connector has third portion that contacts the second electrode, but at a position further away than the first portion, and a fourth portion connected to the second portion. At least a part of the second connector overlaps a part of the first connector between the first lead portion and the second lead portion.

A package includes a leadframe having first surface and a second surface opposing the first surface, the leadframe forming a plurality of leads, a first semiconductor die mounted on the first surface of the leadframe and electrically connected to at least one of the plurality of leads, a second semiconductor die mounted on the second surface of the leadframe, wire bonds electrically connecting the second semiconductor die to the leadframe, and mold compound at least partially covering the first semiconductor die, the second semiconductor die and the wire bonds.

A system and method for manufacturing a packaged component are disclosed. An embodiment comprises forming a plurality of components on a carrier, the plurality of components being separated from each other by kerf regions on a front side of the carrier and forming a metal pattern on a backside of the carrier, wherein the metal pattern covers the backside of the carrier except over regions corresponding to the kerf regions. The method further comprises generating the component by separating the carrier.

A method for manufacturing a semiconductor device includes: fixing a semiconductor chip to a first part of a leadframe; bonding one connector member to a first terminal of the semiconductor chip, a second terminal of the semiconductor chip, a second part of the leadframe, and a third part of the leadframe; forming a sealing member; and separating a first conductive part of the connector member and a second conductive part of the connector member by removing at least a section of the portion of the connector member exposed outside the sealing member, the first conductive part being bonded to the first terminal and the second part, the second conductive part being bonded to the second terminal and the third part.

Techniques are disclosed herein for forming a dual flat no-leads semiconductor package. The techniques begin with a package assembly that includes multiple non-singulated packages. The semiconductor package assembly includes a lead frame assembly having dies coupled thereto. A mold encapsulation covers at least portions of the dies and exposes a plurality of leads. A first cutting step exposes sidewalls of leads of the lead frame. An electroplating step deposits a plating on the exposed leads. A second cutting step cuts through the mold encapsulation aligned with the step cut sidewalls. A third cutting step perpendicular to the step cuts and is made through the lead frame and mold encapsulation to singulate the dies into individual packages.