Patent classifications
H01L2224/45169
Light-emitting device and method of manufacturing the light-emitting device
A light-emitting device includes: a package defining a recess; a light-emitting element mounted on surface that defines a bottom of the recess; and a sealing member disposed in the recess so as to cover the light-emitting element and made of a light-transmissive resin that contains a filler with an average particle diameter of 200 nm or more and 500 nm or less. The sealing member comprises a filler-containing layer, which contains the filler, and a light-transmissive layer that are layered in an order from a bottom side of the recess. The filler-containing layer has a thickness of equal to or larger than a height of the light-emitting element.
Noble metal-coated silver wire for ball bonding, and semiconductor device using noble metal-coated silver wire for ball bonding
A noble metal-coated silver bonding wire for ball bonding wire includes a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes at least one palladium layer, the total palladium content relative to the entire wire is not less than 0.01 mass % and not more than 5.0 mass %, and the total sulfur group element content relative to the entire wire is not less than 0.1 mass ppm and not more than 100 mass ppm.
Noble metal-coated silver wire for ball bonding, and semiconductor device using noble metal-coated silver wire for ball bonding
A noble metal-coated silver bonding wire for ball bonding wire includes a noble metal coating layer on a core material made of pure silver or a silver alloy, wherein the wire contains at least one sulfur group element, the noble metal coating layer includes at least one palladium layer, the total palladium content relative to the entire wire is not less than 0.01 mass % and not more than 5.0 mass %, and the total sulfur group element content relative to the entire wire is not less than 0.1 mass ppm and not more than 100 mass ppm.
INTEGRATED CIRCUIT (IC) PACKAGE WITH A GROUNDED ELECTRICALLY CONDUCTIVE SHIELD LAYER AND ASSOCIATED METHODS
An integrated circuit (IC) package includes a substrate and an IC die carried by the substrate. An encapsulated body is over the IC die. At least one grounding wire is within the encapsulated body and has a proximal end coupled to the substrate and a distal end exposed on an outer surface of the encapsulated body. An electrically conductive shield layer is on the outer surface of the encapsulated body and in contact with the exposed distal end of the at least one grounding wire.
INTEGRATED CIRCUIT (IC) PACKAGE WITH A GROUNDED ELECTRICALLY CONDUCTIVE SHIELD LAYER AND ASSOCIATED METHODS
An integrated circuit (IC) package includes a substrate and an IC die carried by the substrate. An encapsulated body is over the IC die. At least one grounding wire is within the encapsulated body and has a proximal end coupled to the substrate and a distal end exposed on an outer surface of the encapsulated body. An electrically conductive shield layer is on the outer surface of the encapsulated body and in contact with the exposed distal end of the at least one grounding wire.
SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS
A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k−1th semiconductor chip when k is 1.
SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS
A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k−1th semiconductor chip when k is 1.
SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS
A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k+1th semiconductor chip when k is 1.
SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS
A semiconductor package may include: a base layer; first to Nth semiconductor chips (N is a natural number of 2 or more) sequentially offset stacked over the base layer so that a chip pad portion of one side edge region is exposed, wherein the chip pad portion includes a chip pad and includes a redistribution pad that partially contacts the chip pad and extends away from the chip pad; and a bonding wire connecting the chip pad of a kth semiconductor chip among the first to Nth semiconductor chips to the redistribution pad of a k−1th semiconductor chip or a k+1th semiconductor chip when k is a natural number greater than 1 and the bonding wire connecting the chip pad of the kth semiconductor chip to a pad of the base layer or the redistribution pad of the k+1th semiconductor chip when k is 1.
Die bonding material, light-emitting device, and method for producing light-emitting device
The present invention provides a die bonding material containing the following component (A) and a solvent and having a refractive index (nD) at 25° C. of 1.41 to 1.43 and a thixotropic index of 2 or more, a light-emitting device including an adhesive member derived from the die bonding material, and a method for producing the light-emitting device. The die bonding material of the present invention is preferably used for fixing a light emitting element at a predetermined position. Component (A): a curable polysilsesquioxane compound having a repeating unit represented by the following formula (a-1) and satisfying predetermined requirements related to .sup.29Si-NMR and mass average molecular weight (Mw)
R.sup.1-D-SiO.sub.3/2 (a-1) [wherein R.sup.1 represents a fluoroalkyl group represented by a compositional formula: C.sub.mH.sub.(2m−n+1)F.sub.n; m represents an integer of 1 to 10, and n represents an integer of 2 to (2m+1); and D represents a linking group (excluding an alkylene group) for connecting R.sup.1 and Si, or a single bond].