Patent classifications
H01L2224/48177
ASSEMBLY OF FLEXIBLE AND INTEGRATED MODULE PACKAGES WITH LEADFRAMES
Described is a packaged component having a first surface and an opposite second surface. The packaged component may comprise a first element a second element, and a third element. The first element may have a first surface and an opposite second surface. The second element may have a first surface and an opposite second surface. The third element may electrically connect a portion of the first element to a portion of the second element. The second surface of the first element may be adjacent to the second surface of the packaged component, and the second surface of the second element may be adjacent to the second surface of the packaged component.
Semiconductor module
A semiconductor module includes a semiconductor switching element, a multiple of bases, on at least one of which the semiconductor switching element is mounted, a molded resin that seals the semiconductor switching element and the multiple of bases, a multiple of terminals formed integrally with each one of the multiple of bases and provided extending from an outer periphery side face of the molded resin, and a recessed portion or a protruding portion having a depth or a height such that creepage distance between the multiple of terminals is secured, and formed so as to cross an interval between the multiple of terminals, in one portion of the outer periphery side face of the molded resin between the multiple of terminals.
SEMICONDUCTOR DEVICE PACKAGE WITH CONDUCTIVE VIAS AND METHOD OF MANUFACTURING
The present disclosure is directed to embodiments of semiconductor device packages including a plurality of conductive vias and traces formed by an laser-direct structuring process, which includes at least a lasering step and a plating step. First ones of the plurality of conductive vias extend into an encapsulant to contact pads of a die encased within the encapsulant, and second ones of the plurality of conductive vias extend in the encapsulant to end portions of leads in the encapsulant. The second ones of the plurality of conductive vias may couple the leads to contact pads of the die. In some embodiments, the leads of the semiconductor device packages may extend outward and away from encapsulant. In some other alternative embodiments, the leads of the semiconductor device packages may extend outward and away from the encapsulant and then bend back toward the encapsulant such that an end of the lead overlaps a surface of the encapsulant at which the plurality of conductive vias are present.
Semiconductor device manufacturing method and semiconductor device
A semiconductor device includes a semiconductor chip, a substrate having a main surface on which the semiconductor chip is arranged, a resin case which has a storage space therein and a side wall, the side wall having an injection path extending from the storage space to a device exterior, the resin case having a first opening at a bottom side thereof, connecting the storage space to the device exterior, the substrate being disposed on the resin case, at a main surface side of the substrate facing at the bottom side of the resin case, and a sealing material filling the storage space and the injection path.
RING-FRAME POWER PACKAGE
The present disclosure relates to a ring-frame power package that includes a thermal carrier, a spacer ring residing on the thermal carrier, and a ring structure residing on the spacer ring. The ring structure includes a ring body and a number of interconnect tabs that protrude from an outer periphery of the ring body. Herein, a portion of the carrier surface of the thermal carrier is exposed through an interior opening of the spacer ring and an interior opening of the ring body. The spacer ring is not electronically conductive and prevents the interconnect tabs from electrically coupling to the thermal carrier. Each interconnect tab includes a top plated area and a bottom plated area, which is electrically coupled to the top plated area.
HALF-BRIDGE CIRCUIT PACKAGE STRUCTURE
A half-bridge circuit package structure includes a chip pad, a first metal island, a driving chip, an upper bridge switch, and a lower bridge switch. The driving chip includes a ground pad and a high side ground pad. The upper bridge switch includes a first enhancement mode transistor and a first depletion mode transistor. A drain pad of the first depletion mode transistor is electrically connected to the first metal island. The lower bridge switch includes a second enhancement mode transistor and a second depletion mode transistor. A source pad of the second depletion mode transistor is electrically connected to a drain pad of the second enhancement mode transistor. A drain pad of the second depletion mode transistor is electrically connected to the first metal island.
Semiconductor device packaging leadframe assembly and method therefor
A method of manufacturing a semiconductor device is provided. The method includes forming a package leadframe assembly. The package leadframe includes a plurality of leads. An adhesive is placed on a portion of the plurality of leads. A die pad is placed onto the adhesive. A portion of the die pad overlaps the portion of the plurality of leads. A semiconductor die is attached to the die pad. A molding compound encapsulates the semiconductor die and a portion of the package leadframe assembly.
Semiconductor device
An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.
Integrated circuit packaging system with a grid array with a leadframe and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: forming a conductive trace having a terminal end and a circuit end; forming a terminal on the terminal end; connecting an integrated circuit die directly on the circuit end of the conductive trace, the integrated circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end; and forming an insulation layer on the terminal and the integrated circuit die, the integrated circuit die covered by the insulation layer.
SEMICONDUCTOR DEVICE
A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.