Disclosed herein are testing apparatus and methods to identify latent defects in IC devices based on capacitive coupling between bond wires. Bond wires may have latent defects that do not appear as hard shorts or hard opens at the time of testing, but may pose a high risk of developing into hard shorts or hard opens over time. A latent defect may form when two adjacent bond wires are disturbed to become close to each other. According to some embodiments, capacitive coupling between a pair of pins may be used to provide an indication of a near-short latent defect between bond wires connected to the pair of pins.

An object is to provide a power module in which adhesion of a sealing resin is sufficient and which is highly reliable. The power module includes: an insulative board in which a pattern of a conductor layer is formed on a ceramic plate; power semiconductor elements placed on the insulative board; lead frames each in a plate shape connecting from electrodes of the power semiconductor elements to screw-fastening terminal portions; and a sealing resin portion that seals connection portions between the power semiconductor elements and the lead frames, and regions around the connection portions; wherein, in the lead frames, opening portions are formed at positions where each of the lead frames at least partly overlaps, in planar view, with a portion of the insulative board on which the conductor layer is not formed.

Systems, devices, and methods for interconnects for a multi-die package are described. A multi-die package may include a set of conductive pillars and two or more semiconductor dice that each include a bond pad. In some cases, the multi-die package may include a plurality of pillar-wire combinations, and a bond wire may couple a corresponding conductive pillar with a corresponding bond pad. Pillar-wire combinations may each collectively have a matched impedance, or pillar-wire combinations in different groups may have different collective impedances. In other cases, a conductive pillar may be directly coupled with a corresponding bond pad without a bond wire. Different pillar-wire combinations or directly-coupled pillars may carry different signals. In some cases, pillars may be individually impedance-matched to a desired impedance.

A battery system has a battery cell including a can, and a ceramic substrate, including a patterned metallized surface, mounted to the can via a thermally conductive adhesive. The battery system also has a monolithic integrated circuit that measures and transmits data about the cell mounted to the patterned metallized surface such that the ceramic substrate and monolithic integrated circuit are electrically isolated from one another.

A device which enables protection against an abruptly rising pulse such as an electromagnetic pulse in a compact size at a device level and a semiconductor package in which the device is mounted are provided. The semiconductor package (1, 2, 3) includes a substrate (12, 60, 70), an IC chip (21) arranged on the substrate (12, 60, 70), a plurality of connection parts (30) configured to connect the IC chip (21) to the outside, a plurality of bonding wires (40) configured to connect the IC chip (21) and corresponding ones of the plurality of connection parts (30), and a mechanism configured to bypass surge current applied to any of the plurality of connection parts (30) from the connection parts (30) to a ground potential via a path different from the plurality of bonding wires (40).

A power module includes: a plate-shaped thick copper substrate, a conductive stress relaxation metal layer disposed on the thick copper substrate, a semiconductor device disposed on the stress relaxation metal layer, and a plated layer disposed on the stress relaxation metal layer, wherein the semiconductor device is bonded to the stress relaxation metal layer via the plated layer. The thick copper substrate includes a first thick copper layer and a second thick copper layer disposed on the first thick copper layer, and the stress relaxation metal layer is disposed on the second thick copper layer. A part of the semiconductor device is embedded to be fixed to the stress relaxation metal layer. A bonded surface between the semiconductor device and the stress relaxation metal layer are integrated to each other by means of diffusion bonding or solid phase diffusion bonding.

A semiconductor device includes a conductive plate having a front surface on which a semiconductor element is mounted and a sealing resin sealing therein at least the front surface of the conductive plate. The conductive plate includes a structure that traps bubbles in a region where flows of the injected sealing resin merge. The conductive plate has a rectangular shape. The sealing resin is injected from a single inlet on a first longitudinal side of the conductive plate. The region where the flows of the sealing resin merge is a region of a corner of a second longitudinal side that across the semiconductor element, opposes the first longitudinal side from which the sealing resin is injected.

A charger includes a thermal conductive plate for heat dissipation, and a transistor. The transistor includes a drain terminal of a first pulsating voltage level, and a source terminal of a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. The source terminal is disposed closer to the thermal conductive plate than the drain terminal.

The invention concerns an assembly comprising: a fuel supply circuit (15, 15a, 15b) configured to supply fuel to a turbine heat engine, an electronic module (14, 14a, 14b), a power source (13, 13a, 13b) for supplying power to the electronic module (14, 14a, 14b), and a heat exchanger (16, 16a, 16b) positioned to allow a flow of heat from the electronic module (14, 14a, 14b) to the fuel supply circuit (15, 15a, 15b), the assembly being characterised in that the electronic module (14, 14a, 14b) comprises a phase-change material (PCM), configured to change state when the temperature of same reaches a predetermined phase-change temperature (Tf).

Embodiments described herein provide an electronic device having an integrated circuit disposed in a surface mount package. The surface mount integrated circuit package comprises a first pin and a second pin of the integrated circuit configured to couple the integrated circuit to a first terminal and a second terminal disposed on a circuit board. The first pin and second pin define a first connector and a second connector of a differential connector pair in the surface mount integrated circuit package for transferring differential signals from the integrated circuit to the circuit board. The surface mount integrated circuit package comprises an isolation stud disposed between the first pin and the second pin. The isolation stud is disconnected from the integrated circuit and configured to enlarge a gap between the first pin and the second pin relative to respective gaps of other pins coupling the electronic device to the circuit board.