GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.

In many examples, a device comprises a transmitter. The transmitter comprises a power amplifier, a first transformer coil coupled to the power amplifier, and a second transformer coil adapted to be electromagnetically coupled to the first transformer coil. The transmitter also comprises a first bond wire coupled to a first end of the second transformer coil and adapted to be coupled to a first end of an antenna, a capacitor coupled to a second end of the second transformer coil, a switch coupled to the capacitor and configured to engage and disengage the capacitor from the transmitter, and a second bond wire coupled to the switch and adapted to be coupled to a second end of the antenna.

A semiconductor device includes a conductive member including first, second and third conductors mutually spaced, a first semiconductor element having a first obverse surface provided with a first drain electrode, a first source electrode and a first gate electrode, and a second semiconductor element having a second obverse surface provided with a second drain electrode, a second source electrode and a second gate electrode. The first conductor is electrically connected to the first source electrode and the second drain electrode. The second conductor is electrically connected to the second source electrode. As viewed in a first direction crossing the first obverse surface, the second conductor is adjacent to the first conductor in a second direction crossing the first direction. The third conductor is electrically connected to the first drain electrode and is adjacent to the first conductor and the second conductor as viewed in the first direction.

This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.

A semiconductor package includes a die pad, a semiconductor die mounted on the die pad, a plurality of leads including a power lead disposed along a peripheral edge of the die pad, at least one connecting bar connecting the die pad, a power bar disposed on one side of the connecting bar, and a surface mount device (SMD) having a first terminal and a second terminal. The first terminal is electrically connected to the ground level through a first bond wire. The second terminal is electrically connected a power level through a second bond wire.

Disclosed is a conversion element (100). The conversion element (100) comprises: a conversion coating (16), which contains a wavelength-converting conversion material; a first encapsulation coating (30) on a first main surface (20) of the conversion coating, said first encapsulation coating having a thickness of between 10 μm and 500 μm; and a second encapsulation coating (32) on a second main surface (22) of the conversion coating, said second encapsulation coating having a thickness of between 0.1 μm and 20 μm. Also disclosed are an optoelectronic semiconductor component (200) and a method for producing conversion elements.

A semiconductor device includes a source electrode and a drain electrode located over a surface of a semiconductor layer including an electron transit layer and an electron supply layer. A gate electrode is located between the source electrode and the drain electrode. A first diamond layer is located between the source electrode and the drain electrode over the surface with an insulating film therebetween. A second diamond layer is located directly on the surface between the gate electrode and the drain electrode. Of heat generated by the semiconductor layer of the semiconductor device in operation, heat on the side of the electrode on which a relatively strong electric field is applied is efficiently transferred to the second diamond layer. The semiconductor device achieves an excellent heat dissipation property from the semiconductor layer and effectively suppresses overheating and a failure and degradation of the characteristics due to the overheating.

A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.

A semiconductor includes a carrier; a semiconductor element arranged on the carrier; a first row of terminals arranged along a first side face of the carrier; a second row of terminals arranged along a second side face of the carrier opposite the first side face; and an encapsulation body encapsulating the semiconductor element, wherein the semiconductor element comprises a first transistor structure and a second transistor structure, wherein the first row of terminals comprises a first gate terminal, a first sensing terminal coupled, and a first power terminal, wherein the second row of terminals, a second sensing terminal, and a second power terminal.