A semiconductor process for improving loading effects in planarization is provided including steps of forming multiple first protruding patterns on a first region and a second region of a substrate, wherein the pattern density of the first protruding patterns in the first region is larger than the one in the second region, forming a first dielectric layer on the substrate and the first protruding patterns, wherein the first dielectric layer includes multiple second protruding patterns corresponding to the first protruding patterns below, forming a second dielectric layer on the first dielectric layer, performing a first planarization process to remove parts of the second dielectric layer, so that the top surface of the second protruding patterns are exposed, performing an etch process to remove the second protruding patterns of the first dielectric layer, removing the remaining second dielectric layer, and performing another planarization process to the first dielectric layer.

A method of fabricating a semiconductor device includes forming a hard mask layer over a substrate. A multi-layer resist is formed over the hard mask layer. The multi-layer resist is etched to form a plurality of openings in the multi-layer resist to expose a portion of the hard mask layer. Ion are directionally provided at an angle to the multi-layer resist to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In one embodiment, the multi-layer resist is directionally etched by directing etch ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer. In another embodiment, the multi-layer resist is directionally implanted by directing implant ions at an angle to predominately contact sidewalls of the plurality of openings in the multi-layer resist rather than the hard mask layer.

A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A first epitaxial region forms a collector region of a first conductivity type on the collector contact region. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

The present application provides a block copolymer and uses thereof. The block copolymer of the present application exhibits an excellent self-assembling property or phase separation property, and can be provided with a variety of required functions without constraint.

Provided is a method of manufacturing a patterned substrate. The method may be applied to a process of manufacturing a device such as an electronic device or integrated circuit, or another use, for example, to manufacture an integrated optical system, a guidance and detection pattern of a magnetic domain memory, a flat panel display, a LCD, a thin film magnetic head or an organic light emitting diode, and used to construct a pattern on a surface to be used to manufacture a discrete tract medium such as an integrated circuit, a bit-patterned medium and/or a magnetic storage device such as a hard drive.

The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent.

The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.

A semiconductor manufacturing apparatus includes: a stage installed inside a processing chamber and holding a semiconductor substrate having a high-k insulating film including silicate; and a gas supply line including a first system supplying reactive gas to the processing chamber and a second system supplying catalytic gas to the processing chamber, wherein mixed gas which includes complex forming gas reacting with a metal element included in the high-k insulating film to form a first volatile organometallic complex and complex stabilizing material gas increasing stability of the first organometallic complex is supplied as the reactive gas, and catalytic gas using a second organometallic complex, which modifies the high-k insulating film and promotes a formation reaction of the first organometallic complex, as a raw material is supplied.

Methods of and apparatuses for processing substrates having carbon-containing material using atomic layer deposition and selective deposition are provided. Methods involve exposing a carbon-containing material on a substrate to an oxidant and igniting a first plasma at a first bias power to modify a surface of the substrate and exposing the modified surface to an inert plasma at a second bias power to remove the modified surface. Methods also involve selectively depositing a second carbon-containing material onto the substrate. ALE and selective deposition may be performed without breaking vacuum.

A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating layer, a floating gate, a second insulating layer, a control gate and a third insulating layer stacked in this order from a substrate; an erase gate line; and a word line. The logic circuit includes a field effect transistor comprising a gate electrode. The word line includes a protrusion, and a height of the protrusion from the substrate is higher than a height of the erase gate line from the substrate. The word line and the gate electrode are formed of polysilicon.

A planarization method includes providing a substrate having a semiconductor structure formed thereon. A dielectric layer is formed on the substrate, and a mask layer is formed on the dielectric layer. A first chemical mechanical polishing process is performed to remove a portion of the mask layer thereby forming an opening directly over the semiconductor structure and exposing the dielectric layer. A first etching process is performed to anisotropically remove a portion of the dielectric layer from the opening. The mask layer is then removed and a second chemical mechanical polishing process is then performed.