Patent classifications
H01L21/31056
ION BEAM ETCHING
Pattern-multiplication via a multiple step ion beam etching process utilizing multiple etching steps. The ion beam is stationary, unidirectional or non-rotational in relation to the surface being etched during the etching steps, but sequential etching steps can utilize an opposite etching direction. Masking elements are used to create additional masking elements, resulting in decreased spacing between adjacent structures and increased structure density.
Self-aligned shallow trench isolation and doping for vertical fin transistors
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned shallow trench isolation region, including forming a pinch-off layer on one or more vertical fin segments, wherein the pinch-off layer has a thickness on the sidewalls of the one or more vertical fin segments, forming a trench mask layer on predetermined portions of the pinch-off layer, removing portions of the pinch-off layer not covered by the trench mask layer, where the removed portions of the pinch-off layer exposes underlying portions of the substrate, and removing at least a portion of the substrate to form one or more isolation region trenches, where the distance of the sidewall of one of the one or more isolation region trenches to an adjacent vertical fin segment is determined by the thickness of the pinch-off layer.
WAFER LEVEL CURVED IMAGE SENSORS AND METHOD OF FABRICATING THE SAME
A wafer level curved image sensor may include a substrate having a central region, a peripheral region, and an edge region, the peripheral region being formed between the central region and the edge region, supporting patterns formed over the substrate, first fixed patterns formed between the supporting patterns, and an image sensing chip formed over the supporting patterns. The supporting patterns and the first fixed patterns, in combination, form a planar lower surface and a concavely-curved upper surface. The image sensing chip has a curved lower surface and a curved upper surface.
Method of manufacturing a semiconductor device and a semiconductor device
In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
Composition for etching and manufacturing method of semiconductor device using the same
The present invention relates to a composition for etching, comprising a first inorganic acid, a first additive represented by Chemical Formula 1, and a solvent. The composition for etching is a high-selectivity composition that can selectively remove a nitride film while minimizing the etch rate of an oxide film, and which does not have problems such as particle generation, which adversely affect the device characteristics.
ETCHING SUBSTRATES USING ALE AND SELECTIVE DEPOSITION
Methods of and apparatuses for processing substrates having carbon-containing material using atomic layer deposition and selective deposition are provided. Methods involve exposing a carbon-containing material on a substrate to an oxidant and igniting a first plasma at a first bias power to modify a surface of the substrate and exposing the modified surface to an inert plasma at a second bias power to remove the modified surface. Methods also involve selectively depositing a second carbon-containing material onto the substrate. ALE and selective deposition may be performed without breaking vacuum.
METAL ASSISTED CHEMICAL ETCHING FOR FABRICATING HIGH ASPECT RATIO AND STRAIGHT SILICON NANOPILLAR ARRAYS FOR SORTING APPLICATIONS
Techniques relate to forming a sorting device. A mesh is formed on top of a substrate. Metal assisted chemical etching is performed to remove substrate material of the substrate at locations of the mesh. Pillars are formed in the substrate by removal of the substrate material. The mesh is removed to leave the pillars in a nanopillar array. The pillars in the nanopillar array are designed with a spacing to sort particles of different sizes such that the particles at or above a predetermined dimension are sorted in a first direction and the particles below the predetermined dimension are sorted in a second direction.
BLOCK COPOLYMER
The present application relates to a block copolymer and its use. The present application can provides a block copolymer that has an excellent self assembling property or phase separation property and therefore can be used in various applications and its use.
BLOCK COPOLYMER
The present application relates to a block copolymer and its use. The present application can provides a block copolymer that has an excellent self assembling property or phase separation property and therefore can be used in various applications and its use.
BLOCK COPOLYMER
The present application relates to a block copolymer and uses thereof. The present application can provide a block copolymer—which exhibits an excellent self-assembling property and thus can be used effectively in a variety of applications—and uses thereof.