The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.

In one example, a method includes performing a first etching process to pattern a dielectric layer and expose a contact etch stop layer, performing a second etching process to remove the etch stop layer and expose a top surface of an underlying feature, performing a third etching process to laterally recess the etch stop layer, and depositing a conductive material over the underlying feature to create a conductive feature in direct contact with the underlying feature.

A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a polymer block on a corner between the gate structure and the substrate; performing a cleaning process; performing an oxidation process by injecting oxygen gas under 750° C. to form a first seal layer on sidewalls of the gate structure; and forming a source/drain region adjacent to two sides of the gate structure.

Semiconductor device structures are provided. The semiconductor device structure includes a substrate and a first fin structure protruding from the substrate. The semiconductor device structure further includes a gate stack formed across the first fin structure and a first source/drain structure formed over the first fin structure adjacent to the gate stack. The semiconductor device structure further includes a contact structure formed over the first source/drain structure and a dielectric structure formed through the contact structure. In addition, a bottom surface of the contact structure is wider than a top surface of the contact structure.

A plasma processing apparatus 100 is equipped with a shower head 16 and a placing table 2 facing each other. A first RF power supply 10a is configured to apply a RF power to any one of the shower head 16 or the placing table 2 without igniting plasma. A measuring device 204 is configured to measure a physical quantity of the RF power applied by the first RF power supply 10a. A process controller 91 is configured to acquire an inter-electrode distance by using the measured physical quantity of the RF power in a correlation function of the inter-electrode distance and the physical quantity of the RF power.

An etching method includes (a) performing a plasma etching on an organic film, having a mask formed thereon, to form a recess in the organic film; (b) forming an organic protective film on a side wall surface of the recess in the organic film; and (c) performing an additional plasma etching on the organic film after (b).

Embodiments of the present application provide a method for processing a semiconductor structure and a method for forming a semiconductor structure. The method for processing a semiconductor structure includes: providing a semiconductor substrate, the semiconductor substrate being provided with a feature portion, the aspect ratio of the feature portion being greater than a preset aspect ratio, a mask layer being provided on the top of the feature portion; ashing a semiconductor structure, the semiconductor structure comprising the semiconductor substrate, the feature portion, and the mask layer; cleaning the semiconductor structure; drying the semiconductor structure; and removing the mask layer.

The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The method of manufacturing a semiconductor device includes: providing a substrate that includes an array region and an edge region; forming a composite layer on the substrate, where the composite layer includes an amorphous silicon layer and a silicon dioxide layer, and the silicon dioxide layer is located on a surface of the amorphous silicon layer away from the substrate; dry etching the silicon dioxide layer in the array region by using first plasma, to expose a part of the surface of the amorphous silicon layer in the array region; performing, by using second plasma, a plasma surface treatment on an exposed part of the surface of the amorphous silicon layer; cleaning an amorphous silicon layer on which the plasma surface treatment has been performed and a dry etched silicon dioxide layer; and coating a first photoresist layer on the composite layer in the edge region and the array region of the substrate, and performing exposing and developing.

The present invention is a material for forming an adhesive film formed between a silicon-containing middle layer film and a resist upper layer film, the material for forming an adhesive film containing: (A) a resin having a structural unit shown by the following general formula (1); (B) a crosslinking agent containing one or more compounds shown by the following general formula (2); (C) a photo-acid generator; and (D) an organic solvent. This provides: a material for forming an adhesive film in a fine patterning process by a multilayer resist method in a semiconductor device manufacturing process, where the material gives an adhesive film that has high adhesiveness to a resist upper layer film, has an effect of suppressing fine pattern collapse, and that also makes it possible to form an excellent pattern profile; a patterning process using the material; and a method for forming the adhesive film.

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Disclosed is a plasma etching method including a first step of providing a mixed gas containing argon gas and vaporized 1,1,2,2-tetrafluoroethly-2,2,2-trifluoroethyl ether having a molecular structure of a following Chemical Formula 1 to a plasma chamber in which an etching target is disposed; and a second step of etching the etching target using plasma generated from the mixed gas:

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