A method for processing a workpiece, a plasma processing apparatus and a semiconductor device are provided. The method includes placing a workpiece including a spacer layer on a workpiece support in a chamber; selecting a composition modulation gas to modulate a volume ratio of carbon and fluorine to process the workpiece, the composition modulation gas includes one or more molecules, the volume ratio of carbon and fluorine is indicative of a distribution of carbon-based polymer deposited on the spacer layer; generating one or more species using one or more plasmas from a process gas to create a mixture, the process gas includes an etching gas and the composition modulation gas; and exposing the workpiece to the mixture to form a polymer layer on at least a portion of the spacer layer and to etch at least a portion of the spacer layer.

An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.

The present invention aims to provide a dry etching agent having less load on global environment and capable of anisotropic etching without the use of special equipment and obtaining a good processing shape and to provide a dry etching method using the dry etching agent. The dry etching agent according the present invention contains at least a hydrofluoroalkylene oxide represented by the following chemical formula: CF.sub.3—C.sub.xH.sub.yF.sub.zO (where x=2 or 3; y=1, 2, 3, 4 or 5; and z=2x−1−y) and having an oxygen-containing three-membered ring. The dry etching method according to the present invention includes selectively etching of at least one kind of silicon-based material selected from the group consisting of silicon dioxide, silicon nitride, polycrystalline silicon, amorphous silicon and silicon carbide with the use of a plasma gas generated by plasmatization of the dry etching agent.

Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

A plasma etching method using a Faraday cage, which effectively produces a blazed grating pattern.

A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.

Disclosed are DRAM devices and methods of forming DRAM devices. One method may include forming a plurality of trenches and angled structures, each angled structure including a first sidewall opposite a second sidewall, wherein the second sidewall extends over an adjacent trench. The method may include forming a spacer along a bottom surface of the trench, along the second sidewall, and along the first sidewall, wherein the spacer has an opening at a bottom portion of the first sidewall. The method may include forming a drain in each of the angled structures by performing an ion implant, which impacts the first sidewall through the opening at the bottom portion of the first sidewall. The method may include removing the spacer from the first sidewall, forming a bitline over the spacer along the bottom surface of each of the trenches, and forming a series of wordlines along the angled structures.

In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

A method for forming a semiconductor device is provided. The method includes the following steps: providing a semiconductor substrate; forming a pad layer on the semiconductor substrate; forming a first passivation layer on the pad layer; forming a second passivation layer on the first passivation layer, wherein the second passivation layer comprises polycrystalline silicon; forming an oxide layer on the second passivation layer; forming a nitride layer on the oxide layer; removing a portion of the oxide layer and a portion of the nitride layer to expose a portion of the second passivation layer; removing the portion of the second passivation layer that has been exposed to expose a portion of the first passivation layer; and removing the portion of the first passivation layer that has been exposed to expose a portion of the pad layer.

A method may include providing a set of features in a mask layer, wherein a given feature comprises a first dimension along a first direction, second dimension along a second direction, orthogonal to the first direction, and directing an angled ion beam to a first side region of the set of features in a first exposure, wherein the first side region is etched a first amount along the first direction. The method may include directing an angled deposition beam to a second side region of the set of features in a second exposure, wherein a protective layer is formed on the second side region, the second side region being oriented perpendicularly with respect to the first side region. The method may include directing the angled ion beam to the first side region in a third exposure, wherein the first side region is etched a second amount along the first direction.