A method for forming features over a wafer with a carbon based deposition is provided. The carbon based deposition is pretuned, wherein the pretuning causes a non-uniform removal of some of the carbon based deposition. An oxide deposition is deposited through an atomic layer deposition process, wherein the depositing the oxide deposition causes a non-uniform removal of some of the carbon based deposition. At least one additional process is provided, wherein the at least one additional process completes formation of features over the wafer, wherein the features are more uniform than features that would be formed without pretuning.

Analog and logic devices may coexist on a common integrated circuit chip, accommodating features with different pitches, linewidths, and pattern densities. Such differences in design and layout at various layers during manufacturing can cause process loading by contributing different amounts of reactants to surface chemical reactions. Such variation in the balance of chemical reactants can result in disparities in film thicknesses within the chip that can affect device performance. Embodiments of the present disclosure disclose a masking sequence that can alleviate process loading disparities during an undercut etch process adjacent to polysilicon structures.

A method for forming a stair-step structure in a stack on a substrate is provided. The method comprises at least one stair step cycle. Each stair step cycle comprises trimming the mask and etching the stack. Etching the stack is provided in a plurality of cycles wherein each cycle comprises etching a SiO.sub.2 layer and etching a SiN layer. Etching a SiO.sub.2 layer comprises flowing a SiO.sub.2 etching gas into the plasma processing chamber, wherein the SiO.sub.2 etching gas comprises a hydrofluorocarbon, an inert bombardment gas, and at least one of SF.sub.6 and NF.sub.3, generating a plasma from the SiO.sub.2 etching gas, providing a bias, and stopping the SiO.sub.2 layer etch. The etching a SiN layer comprises flowing a SiN etching gas into the plasma processing chamber, comprising a hydrofluorocarbon and oxygen, generating a plasma from the SiN etching gas, providing a bias, and stopping the SiN layer etch.

An etching method includes forming a protective layer containing a tin atom on a surface of a substrate. The substrate has a region to be etched and a mask provided on the region. The etching method further includes etching the region in the substrate using the mask.

In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Removing a stimuli responsive polymer (SRP) from a substrate includes controlled degradation. In certain embodiments of the methods described herein, removing SRPs includes exposure to two reactants that react to form an acid or base that can trigger the degradation of the SRP. The exposure occurs sequentially to provide more precise top down control. In some embodiments, the methods involve diffusing a compound, or a reactant that reacts to form a compound, only to a top portion of the SRP. The top portion is then degraded and removed, leaving the remaining SRP intact. The exposure and removal cycles are repeated.

Removing stimulus responsive polymers (SRPs) includes exposure to high energy metastable species, generated in a noble gas plasma, at an elevated temperature. The metastable species have sufficient energies and lifetimes to scission bonds on the polymer or other residues. At temperatures greater than the ceiling temperature of the SRP, there is a strong thermodynamic driving force to revert to volatile monomers once bond scissioning has occurred. The metastable species are not chemically reactive and do not appreciably affect the underlying surface. The high energy metastable species are effective at removing residues that remain after exposure to other stimuli such as heat.

A resist underlayer film forming composition capable of forming a flat film that exhibits high etching resistance, a good dry etching rate ratio and a good optical constant, while having good coverage even with respect to a so-called multileveled substrate and having a small difference in the film thickness after embedding. Also, a method for producing a polymer that is suitable for the resist underlayer film forming composition; a resist underlayer film which uses the resist underlayer film forming composition; and a method for producing a semiconductor device. This resist underlayer film forming composition contains: a reaction product of an aromatic compound (A) that has from 6 to 120 carbon atoms, and a compound that is represented by formula (1); and a solvent.

A method for manufacturing a semiconductor device, including the steps of forming a semiconductor over a substrate; forming a first conductor over the semiconductor; forming a first insulator over the first conductor; forming a resist over the first insulator; performing light exposure and development on the resist to make a second region and a third region remain and expose part of the first insulator; applying a bias in a direction perpendicular to a top surface of the substrate and generating plasma using a gas containing carbon and halogen; and depositing and etching an organic substance with the plasma. The etching rate of the organic substance is higher than the deposition rate of the organic substance in an exposed part of the first insulator, and the deposition rate of the organic substance is higher than the etching rate of the organic substance in a side surface of the second region.

A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.