In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor device etching equipment. The semiconductor structure manufacturing method includes: providing a semiconductor structure to be processed, putting the semiconductor structure to be processed in a processing chamber, wherein the semiconductor structure to be processed includes a substrate and target structures to be processed located on the substrate, and sidewalls of the target structures to be processed are covered with bromine-containing polymer layers; removing the bromine-containing polymer layers, and forming a semiconductor structure; and removing products resulting from a process of removing the bromine-containing polymer layers from the processing chamber.

A method for making a semiconductor device includes patterning at least one dielectric layer disposed over a conductive cap layer to form a via opening penetrating through the at least one dielectric layer to expose the conductive cap layer and to form a top portion of the conductive cap layer into a metal oxide layer; converting the metal oxide layer to a metal oxynitride layer by a soft ashing process using a processing gas containing nitrogen gas; removing the metal oxynitride layer from a remaining portion of the conductive cap layer; and forming a via contact in the via opening to electrically connect the remaining portion of the conductive cap layer.

A wafer chuck assembly includes a puck, a shaft and a base. The puck includes an electrically insulating material that defines a top surface of the puck; a plurality of electrodes are embedded within the electrically insulating material. The puck also includes an inner puck element that forms one or more channels for a heat exchange fluid, the inner puck element being in thermal communication with the electrically insulating material, and an electrically conductive plate disposed proximate to the inner puck element. The shaft includes an electrically conductive shaft housing that is electrically coupled with the plate, and a plurality of connectors, including electrical connectors for the electrodes. The base includes an electrically conductive base housing that is electrically coupled with the shaft housing, and an electrically insulating terminal block disposed within the base housing, the plurality of connectors passing through the terminal block.

In an embodiment, a method includes: receiving, within a processing chamber, a wafer with a photoresist mask above a metal layer, wherein the processing chamber is connected to a gas source; applying an etchant configured to etch the metal layer in accordance with the photoresist mask within the processing chamber; and applying gas from the gas source to perform plasma ashing in the processing chamber.

A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.

In one embodiment, a system includes an RF source and an RF impedance matching circuit receiving RF power from the RF source. The matching circuit includes at least one variable reactance element, a sensor operably coupled to a component of the matching circuit, and a control circuit. The control circuit receives a signal from the sensor indicative of a parameter value. Upon determining the parameter value meets a first predetermined condition, the control circuit transmits a control signal to the RF source causing the RF source to carry out a power control scheme. The power control scheme causes the RF source to reduce or maintain the RF power without turning off the RF power.

A substrate processing system for selectively etching a substrate includes a first chamber and a second chamber. A first gas delivery system supplies an inert gas species to the first chamber. A plasma generating system generates plasma including ions and metastable species in the first chamber. A gas distribution device removes the ions from the plasma, blocks ultraviolet (UV) light generated by the plasma and delivers the metastable species to the second chamber. A substrate support is arranged below the gas distribution device to support the substrate. A second gas delivery system delivers a reactive gas species to one of the gas distribution device or a volume located below the gas distribution device. The metastable species transfer energy to the reactive gas species to selectively etch one exposed material of the substrate more than at least one other exposed material of the substrate.

Aspects of this disclosure relate to selective removal of material of a layer, such as a carbon-containing layer. The layer can be over a patterned structure of two different materials. Treating the layer to cause the removal agent to be catalytically activated by a first area of the patterned structure to remove material of the organic material over the first area at a greater rate than over a second area of the patterned structure having a different composition from the first area.

A method of manufacturing chips includes a preparing step of preparing a wafer unit in which a wafer having a plurality of devices formed thereon is affixed to a tape with a die-attach layer being interposed therebetween, the die-attach layer including fillers, and the devices are protected by a protective member and a face side of the wafer is exposed along the projected dicing lines, a wafer processing step of performing plasma etching on the wafer from the face side thereof to divide the wafer and expose the die-attach layer along the projected dicing lines, a die-attach layer processing step of performing plasma etching on the die-attach layer from the face side of the wafer, and a cleaning step of ejecting a fluid to the face side of the wafer to remove filler residuals along the projected dicing lines from the wafer unit.