A method of forming a semiconductor device includes forming a first dummy gate structure and a second dummy gate structure over a fin; forming a first dielectric layer around the first dummy gate structure and around the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure to form a first recess and a second recess in the first dielectric layer, respectively; forming a gate dielectric layer in the first recess and the second recess; forming a first work function layer over the gate dielectric layer in the first and the second recesses; removing the first work function layer from the first recess; converting a surface layer of the first work function layer in the second recess into an oxide; and forming a second work function layer in the first recess over the gate dielectric layer and in the second recess over the oxide.

In one embodiment, a method of matching an impedance is disclosed. An impedance matching network is coupled between a radio frequency (RF) source and a plasma chamber. The matching network includes a variable reactance element (VRE) having different positions for providing different reactances. The RF source has an RF source control circuit carrying out a power control scheme to control a power delivered to the matching network. Based on a determined parameter, a new position for the VRE is determined to reduce a reflected power at the RF input of the matching network. The matching network provides a notice signal to the RF source indicating the VRE will be altered. In response to the notice signal, the RF source control circuit alters the power control scheme. While the power control scheme is altered, the VRE is altered to the new position.

A processing method includes: disposing a workpiece in a processing container of a processing apparatus, and maintaining an inside of the processing container in a vacuum state; providing a cluster nozzle in the processing container; supplying a cluster generating gas to the cluster nozzle and adiabatically expanding the cluster generating gas in the cluster nozzle, thereby generating gas clusters; generating plasma in the cluster nozzle to ionize the gas clusters and injecting the ionized gas clusters onto the workpiece; supplying a reactive gas to the cluster nozzle and exposing the reactive gas to the plasma such that the reactive gas becomes monomer ions or radicals; and supplying the monomer ions or radicals to the processing container, thereby exerting a chemical reaction on a substance present on a surface of the workpiece.

Provided is a plasma processing method capable of improving an etching selectivity of a material to be etched with respect to a mask material and reducing a roughness of a side wall of a mask pattern. The plasma processing method of selectively depositing a deposition film on the mask material with respect to the material to be etched includes controlling an etching parameter so that an incubation time of the mask material is shorter than an incubation time of the material to be etched.

A method which includes providing a substrate having a source/drain region and an etch stop layer on the source/drain region. A plasma etching process is performed using an etching gas that removes the etch stop layer and forms a sacrificial oxide capping layer on the source/drain region. The sacrificial oxide capping layer is then from the source/drain region.

An integrated circuit device according to the inventive concepts includes lower wiring structures formed on a substrate, an air gap arranged between the lower wiring structures, a capping layer covering an upper surface of the air gap, an etch stop layer conformally covering an upper surfaces of the lower wiring structures and the capping layer and having a protrusion and recess structure, an insulating layer covering the etch stop layer, and an upper wiring structure penetrating the insulating layer and connected to the upper surface of the lower wiring structure not covered with the etch stop layer, wherein the upper wiring structure covers a portion of an upper surface of the capping layer, and a level of the upper surface of the capping layer is higher than a level of the upper surface of the lower wiring structures.

A wafer chuck assembly includes a puck, a shaft and a base. The puck includes an electrically insulating material that defines a top surface of the puck; a plurality of electrodes are embedded within the electrically insulating material. The puck also includes an inner puck element that forms one or more channels for a heat exchange fluid, the inner puck element being in thermal communication with the electrically insulating material, and an electrically conductive plate disposed proximate to the inner puck element. The shaft includes an electrically conductive shaft housing that is electrically coupled with the plate, and a plurality of connectors, including electrical connectors for the electrodes. The base includes an electrically conductive base housing that is electrically coupled with the shaft housing, and an electrically insulating terminal block disposed within the base housing, the plurality of connectors passing through the terminal block.

A technique for suppressing a metal component from remaining at a bottom of a mask pattern when the mask pattern is formed using a metal-containing resist film. A developable anti reflection film 103 is previously formed below a resist film 104. Further, after exposing and developing the wafer W, TMAH is supplied to the wafer W to remove a surface of the anti-reflection film 103 facing a bottom of the recess pattern 110 of the resist film 104. Therefore, the metal component 105 can be suppressed from remaining at the bottom of the recess pattern 110. Therefore, when the SiO.sub.2 film 102 is subsequently etched using the pattern of the resist film 104, the etching is not hindered, so that defects such as bridges can be suppressed.

Implementations of die singulation systems and related methods may include forming a plurality of die on a first side of a substrate, forming a backside metal layer on a second side of a substrate, applying a photoresist layer over the backside metal layer, patterning the photoresist layer along a die street of the substrate, and forming a groove at the pattern of the photoresist layer only partially through a thickness of the backside metal layer. The groove may be located in the die street of the substrate. The method may also include etching through a remaining portion of the backside metal layer located in the die street, removing the photoresist layer, and singulating the plurality of die included in the substrate by removing substrate material in the die street.

An etching method includes (a) performing a plasma etching on an organic film, having a mask formed thereon, to form a recess in the organic film; (b) forming an organic protective film on a side wall surface of the recess in the organic film; and (c) performing an additional plasma etching on the organic film after (b).