A target object processing method is provided for processing a target object using a plasma processing apparatus including a processing chamber, a mounting table which is disposed in the processing chamber and on which the target object is mounted, an outer peripheral member disposed around the mounting table, and a first voltage application device configured to apply a voltage to the outer peripheral member. The method comprises preparing the target object having an etching target film and a patterned mask formed on the etching target film, and processing the mask. The step of processing the mask includes supplying a first processing gas containing a first rare gas to the processing chamber, and a first plasma processing for processing the mask positioned at an outer peripheral portion of the target object using plasma of the first processing gas while applying a DC voltage to the outer peripheral member.

In a method of manufacturing a semiconductor device, underlying structures comprising gate electrodes and source/drain epitaxial layers are formed, one or more layers are formed over the underlying structures, a hard mask layer is formed over the one or more layers, one or more first resist layers are formed over the hard mask layer, a first photo resist pattern is formed over the one or more first resist layers, a width of the first photo resist pattern is adjusted, the one or more first resist layers are patterned by using the first photo resist pattern as an etching mask, thereby forming a first hard mask pattern, and the hard mask layer is patterned by using the first hard mask pattern, thereby forming a second hard mask pattern.

An interconnect structure, along with methods of forming such, are described. In some embodiments, the method includes forming a first dielectric layer over one or more devices, forming a first conductive feature in the first dielectric layer, and forming two dielectric features over the first dielectric layer and the first conductive feature. At least one of the two dielectric features has a first width, and each dielectric feature includes a first low-k dielectric layer, an oxide layer, and a first etch stop layer. The method further includes forming a second conductive feature between the two dielectric features, and the second conductive feature has a second width substantially the same as the first width.

An etching method of the invention includes: a resist pattern-forming step of forming a resist layer on a target object, the resist layer being formed of a resin, the resist layer having a resist pattern; an etching step of etching the target object via the resist layer having the resist pattern; and a resist protective film-forming step of forming a resist protective film on the resist layer. The etching step is repetitively carried out multiple times. After the etching steps are repetitively carried out multiple times, the resist protective film-forming step is carried out.

A semiconductor device includes a substrate having a first region and a second region of opposite conductivity types, an isolation feature over the substrate, a first fin protruding from the substrate and through the isolation feature in the first region, a first epitaxial feature over the first fin, a second fin protruding from the substrate and through the isolation feature in the second region, and a second epitaxial feature over the second fin. A portion of the isolation feature located between the first fin and the second fin protrudes from a top surface of the isolation feature.

In one embodiment, a method of matching an impedance is disclosed. An impedance matching network is coupled between a radio frequency (RF) source and a plasma chamber. The matching network includes a variable reactance element (VRE) having different positions for providing different reactances. The RF source is subject to a power control scheme to control a power delivered to the matching network. Based on a determined parameter, a new position for the VRE is determined to reduce a reflected power at the RF input of the matching network. The VRE is altered to the new position while the power control scheme is altered.

Provided are a substrate processing apparatus and a substrate processing method capable of achieving uniform trimming throughout an entire surface of a substrate. The substrate processing apparatus includes a gas channel including a center gas inlet and an additional gas inlet spaced apart from the center gas inlet, and a shower plate including a plurality of holes connected to the center gas inlet and the additional gas inlet, wherein a gas flow channel is formed having a clearance defined by a lower surface of the gas channel and an upper surface of the shower plate, the lower surface and the upper surface being substantially parallel.

The present invention provides a resist underlayer film capable of improving LWR and CDU in a fine pattern formed by a chemically-amplified resist which uses an acid as a catalyst. A composition for forming a silicon-containing resist underlayer film, including a thermosetting silicon-containing material (Sx), a curing catalyst (Xc), and a solvent, in which a distance of diffusion of the curing catalyst (Xc) from a resist underlayer film formed from the composition for forming a silicon-containing resist underlayer film to a resist upper layer film to be formed on the resist underlayer film is 5 nm or less.

Provided is a manufacturing method for a semiconductor device including forming a first electrode layer on a front surface of a wafer, implanting, into an outer peripheral region of the front surface of the wafer, a heavy ion of an element in third and subsequent rows of a periodic table, forming an oxide film in the outer peripheral region into which the heavy ion has been implanted, and forming a second electrode layer on the first electrode layer by plating. A dose of the heavy ion may be 1E15 cm.sup.−2 or more. A depth of an implantation range of the heavy ion into the wafer may be 0.02 μm or more. The heavy ion may be an As ion, a P ion, or an Ar ion.

A method of detecting a deviation amount of a substrate transport position includes: setting a temperature of a substrate support surface to the same temperature over an entire substrate support surface; etching a first etching target film formed on a substrate; acquiring a first etching rate that is an etching rate of the first etching target film; setting the temperature of the substrate support surface to be concentrically and gradually increased from a central portion to a peripheral edge portion; etching a second etching target film formed on the substrate, the second etching target film being same kind as the first etching target film; acquiring a second etching rate that is an etching rate of the second etching target film; calculating a difference between the acquired first etching rate and second etching rate; and calculating the deviation amount of the substrate transport position based on the calculated difference.