Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.

Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.

Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1 feature and at least one wider than 1 feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1 feature and at least one wider than 1 feature; the first metal material is reflowed such that the at least one 1 feature is filled with the first metal material and the at least one wider than 1 feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1 feature is filled with the second metal material.

In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, first layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.

A method of manufacturing a semiconductor device includes preparing an object layer on a substrate; polishing the object layer with a first slurry including a first abrasive having a zeta potential of a first polarity; rinsing a surface of the object layer, using a rinsing solution including a chemical of a second polarity, opposite to the first polarity; and polishing the object layer with a second slurry including a second abrasive having a zeta potential of a second polarity, opposite to the first polarity.

The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching. The present invention further provides a semiconductor structure forming method, comprising: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas; removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas; removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.

Methods and apparatus for creating a dual metal interconnect on a substrate. In some embodiments, a first liner of a first nitride material is deposited into at least one 1X feature and at least one wider than 1X feature, the first liner has a thickness of less than or equal to approximately 12 angstroms; a second liner of a first metal material is deposited into the at least one 1X feature and at least one wider than 1X feature; the first metal material is reflowed such that the at least one 1X feature is filled with the first metal material and the at least one wider than 1X feature remains unfilled with the first metal material; a second metal material is deposited on the first metal material, and the second metal material is reflowed such that the at least one wider than 1X feature is filled with the second metal material.

The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching. The present invention further provides a semiconductor structure forming method, comprising: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas; removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas; removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

The invention discloses an electrochemical mechanical polishing/planarization equipment for processing a polishing surface of a conductive wafer substrate, which includes a power supply; a polishing table with conductivity; a polishing pad including an insulating active layer and having holes where a conductive chemical liquid is accommodated; a polishing head having conductivity and being attached to the back of the polishing surface. The power supply, the polishing table, the chemical liquid, the conductive wafer substrate, and the polishing head in sequence form a conductive loop, and an electrochemical reaction layer is formed on the polishing surface of the conductive wafer substrate. The polishing head drives the wafer substrate to move relative to the polishing pad, and to implement a mechanical polishing or a chemical mechanical polishing of the electrochemical reaction layer.