The invention discloses an electrochemical mechanical polishing/planarization equipment for processing a polishing surface of a conductive wafer substrate, which includes a power supply; a polishing table with conductivity; a polishing pad including an insulating active layer and having holes where a conductive chemical liquid is accommodated; a polishing head having conductivity and being attached to the back of the polishing surface. The power supply, the polishing table, the chemical liquid, the conductive wafer substrate, and the polishing head in sequence form a conductive loop, and an electrochemical reaction layer is formed on the polishing surface of the conductive wafer substrate. The polishing head drives the wafer substrate to move relative to the polishing pad, and to implement a mechanical polishing or a chemical mechanical polishing of the electrochemical reaction layer.

A surface planarization system is presented. The system comprises an external energy source for generating a localized energy distribution within a processing region, and a control unit for operating the external energy source to create, by the localized energy distribution, a predetermined temperature pattern within the processing region such that different locations of the processing region are subjected to different temperatures. This provides that when a sample (e.g. semiconductor wafer) during its interaction with an etching material composition is located in the processing region, the temperature pattern at different locations of the sample's surface creates different material removal rates by the etching material composition (different etch rates).

In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a conductive material in the trench and over a top surface of the material layer and polishing the conductive material with a slurry to expose the top surface of the material layer and to form a conductive structure in the trench. The method for forming a semiconductor structure further includes forming a material layer over a substrate and forming a trench in the material layer. The method for forming a semiconductor structure further includes removing the slurry with a reducing solution. In addition, the reducing solution includes a reducing agent, and a standard electrode voltage of the conductive material is greater than a standard electrode voltage of the reducing agent.

Exemplary substrate electrochemical planarization apparatuses may include a chuck body defining a substrate support surface. The apparatuses may include a retaining wall extending from the chuck body. The apparatuses may include an electrolyte delivery port disposed radially inward of the retaining wall. The apparatuses may include a spindle that is positionable over the chuck body. The apparatuses may include an end effector coupled with a lower end of the spindle. The end effector may be conductive. The apparatuses may include an electric contact extending from the chuck body or retaining wall. The apparatuses may include a current source. The current source may be configured to provide an electric current to an electrolyte within an open interior defined by the retaining wall.

Methods for forming semiconductor structures are provided. The method for forming a semiconductor structure includes forming a conductive material in the trench and over a top surface of the material layer and polishing the conductive material with a slurry to expose the top surface of the material layer and to form a conductive structure in the trench. The method for forming a semiconductor structure further includes forming a material layer over a substrate and forming a trench in the material layer. The method for forming a semiconductor structure further includes removing the slurry with a reducing solution. In addition, the reducing solution includes a reducing agent, and a standard electrode voltage of the conductive material is greater than a standard electrode voltage of the reducing agent.

A method of manufacturing a semiconductor device includes preparing an object layer on a substrate; polishing the object layer with a first slurry including a first abrasive having a zeta potential of a first polarity; rinsing a surface of the object layer, using a rinsing solution including a chemical of a second polarity, opposite to the first polarity; and polishing the object layer with a second slurry including a second abrasive having a zeta potential of a second polarity, opposite to the first polarity.

A chemical mechanical planarization (CMP) apparatus is provided. The CMP apparatus includes at least one platen; and a polishing pad disposed on the platen. The CMP apparatus also includes a polishing head disposed above the platen and configured to clamp a to-be-polished wafer; and a basic solution supply port disposed above the platen and configured to supply a basic solution onto a surface of the polishing pad. Further, the CMP apparatus includes a slurry arm disposed above the platen and configured to supply a polish slurry on the surface of the polishing pad; and a deionized water supply port configured to supply deionized water onto the surface of the polishing pad. Further, the CMP apparatus also includes a negative power source configured to apply a negative voltage onto the surface of the polishing pad.

In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, first layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.

A surface planarization system is presented. The system comprises an external energy source for generating a localized energy distribution within a processing region, and a control unit for operating the external energy source to create, by the localized energy distribution, a predetermined temperature pattern within the processing region such that different locations of the processing region are subjected to different temperatures. This provides that when a sample (e.g. semiconductor wafer) during its interaction with an etching material composition is located in the processing region, the temperature pattern at different locations of the sample's surface creates different material removal rates by the etching material composition (different etch rates).