The present disclosure provides an array substrate and a manufacturing method of the array substrate. In the manufacturing method of the array substrate, during performing a first wet etching and a second wet etching on a second metal layer, the wet etching is stopped when a copper conductive layer is merely etched completely. Because a wet etching speed of a liner layer is slow, an etching time of the wet etching and a CD loss of the copper conductive layer can be greatly reduced, and the CD loss is relatively small. Meanwhile, an entire CD loss of the second metal layer can be reduced, and an aperture ratio can be improved.

The present invention relates to an aqueous chemical composition C for removing from a substrate selectively under heat residues of a nickel-platinum alloy containing at least 8% by weight of Pt compared to the total weight of nickel-platinum alloy, characterised in that it is prepared by mixing a composition B comprising bromide ions and a composition H comprising hydrogen peroxide such that in the composition C, at the moment of mixing, the molar concentration of bromide ions is comprised between 0.15 mol/L and 0.45 mol/L and the molar ratio of hydrogen peroxide with respect to bromide ions is comprised between 1.1 and 2.

The invention also pertains to a method for selectively removing nickel-platinum alloy residues containing at least 8% by weight of Pt compared to the total weight of nickel-platinum alloy from a substrate, comprising the following steps: preparing under heat a chemical composition C according to any one of claims 1 to 3, placing the hot chemical composition C and the substrate in contact for a sufficient duration to remove the nickel-platinum alloy residues from the substrate.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method of manufacture comprises receiving a substrate including a semiconductor material stack formed thereon, wherein the semiconductor material stack includes a first semiconductor layer of a first semiconductor material and second semiconductor layer of a second semiconductor material that is different than the first semiconductor material. Patterning the semiconductor material stack to form a trench. The patterning includes performing a first etch process with a first etchant for a first duration and then performing a second etch process with a second etchant for a second duration, where the second etchant is different from the first etchant and the second duration is greater than the first duration. The first etch process and the second etch process are repeated a number of times. Then epitaxially growing a third semiconductor layer of the first semiconductor material on a sidewall of the trench.

The present disclosure provides a non-isothermal wet atomic layer etch (ALE) process for etching polycrystalline materials, such as metals, metal oxides and silicon-based materials, formed on a substrate. More specifically, the present disclosure provides various embodiments of methods that utilize thermal cycling in a wet ALE process to independently optimize the reaction temperatures utilized within individual processing steps of the wet ALE process. Like conventional wet ALE processes, the wet ALE process described herein is a cyclic process that includes multiple cycles of surface modification and dissolution steps. Unlike conventional wet ALE processes, however, the wet ALE process described herein is a non-isothermal process that performs the surface modification and dissolution steps at different temperatures. This allows independent optimization of the surface modification and dissolution reactions.

Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC comprises a substrate. A resistor overlies the substrate. The resistor comprises a resistive structure overlying the substrate. The resistor also comprises a conductive contact overlying and electrically coupled to the resistive structure. A capping structure is disposed over the conductive contact, wherein the capping structure extends laterally over an upper surface of the conductive contact and vertically along a first sidewall of the conductive contact, such that a lower surface of the capping structure is disposed below a lower surface of the conductive contact.

A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

A treatment liquid contains water, hydroxylamine, and one or more kinds of hydrazines selected from the group consisting of hydrazine, a hydrazine salt, and a hydrazine derivative, in which a total content of the hydrazines is 1 part by mass or less with respect to 100 parts by mass of the hydroxylamine.

A system for assembling fields from a source substrate onto a second substrate. The source substrate includes fields. The system further includes a transfer chuck that is used to pick at least four of the fields from the source substrate in parallel to be transferred to the second substrate, where the relative positions of the at least four of the fields is predetermined.

Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.